Write buffer-aware address mapping for NAND flash memory devices

Abstract

By using small-sized, next-generation NVRAM (such as MRAM, FeRAM and PRAM) as a write buffer, we can improve the overall performance of the NAND flash memorybased storage systems. However, traditional address mapping algorithms in Flash Translation Layer (FTL) software were designed without any consideration of the existence of write buffer. In this paper, we propose a novel write buffer-aware flash translation layer algorithm, optimistic FTL, which is designed to harmonize well with NVRAM write buffers. Simulation results show that the proposed optimistic FTL outperforms previous log block-based FTL algorithms.