Er and Pt gate electrodes formed on SiO2 gate dielectrics
- Authors
- Choi, Chel-Jong; Jung, Won-Jin; Kim, Yark-Yeon; Jun, Myung-Sim; Kim, Tae-Youb; Jang, Moon-Gyu; Song, Myeong-Ho; Lee, Seong-Jae
- Issue Date
- Nov-2007
- Publisher
- ELECTROCHEMICAL SOC INC
- Citation
- ELECTROCHEMICAL AND SOLID STATE LETTERS, v.11, no.2, pp.H22 - H25
- Indexed
- SCIE
SCOPUS
- Journal Title
- ELECTROCHEMICAL AND SOLID STATE LETTERS
- Volume
- 11
- Number
- 2
- Start Page
- H22
- End Page
- H25
- URI
- https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/172213
- DOI
- 10.1149/1.2812433
- ISSN
- 1099-0062
- Abstract
- We investigated the electrical and structural properties of W/Er/SiO2 and Pt/SiO2 gate stacks. W/Er/SiO2 gate stacks exhibited increased capacitance after rapid thermal annealing (RTA) process while the capacitance of Pt/SiO2 gate stacks remained unchangeable regardless of RTA process. Because of the physical plasma damage that occurred during the sputtering deposition process, Pt penetration led to a decrease in the SiO2 film thickness of Pt/SiO2 gate stacks. This resulted in the reduction of the equivalent oxide thickness compared to the poly-Si/SiO2 gate stack. A relatively small flatband voltage shift of W/Er/SiO2 gate stacks was attributed to the reduction of effective oxide charge caused by interfacial reaction between Er and SiO2 films.
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