An efficient load balancing method for multi-core systems with asymmetric memory architectures
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Byung-Jin | - |
dc.contributor.author | Hwang, Young-Si | - |
dc.contributor.author | Ahn, Young-Ho | - |
dc.contributor.author | Chung, Ki-Seok | - |
dc.date.accessioned | 2022-12-20T10:45:54Z | - |
dc.date.available | 2022-12-20T10:45:54Z | - |
dc.date.created | 2022-09-16 | - |
dc.date.issued | 2010-12 | - |
dc.identifier.issn | 0000-0000 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/173322 | - |
dc.description.abstract | As the number of cores in a processor increases, asymmetrically distributed memory architecture is expected to become widely adopted. Running an application program in a distributed fashion on an asymmetric memory architecture effectively is a challenging task. In this paper, we propose a novel load balancing technique for multi-core systems with asymmetric memory architectures. The proposed method uses probabilistic information on the expected execution time of the child processes for each parent process. Also, to maximize the load balancing effect with low cost, the proposed method groups processes, and treats each group as a load balancing unit. The trade-off between load balancing effect of each load balancing unit and the cost is taken into account. To show the effectiveness of this paper, we present test cases in which the proposed method show better performance than that of existing load balancing methods. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEEE | - |
dc.title | An efficient load balancing method for multi-core systems with asymmetric memory architectures | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Chung, Ki-Seok | - |
dc.identifier.doi | 10.1109/ICNIDC.2010.5657935 | - |
dc.identifier.scopusid | 2-s2.0-78651339193 | - |
dc.identifier.bibliographicCitation | Proceedings - 2010 2nd IEEE International Conference on Network Infrastructure and Digital Content, IC-NIDC 2010, pp.944 - 947 | - |
dc.relation.isPartOf | Proceedings - 2010 2nd IEEE International Conference on Network Infrastructure and Digital Content, IC-NIDC 2010 | - |
dc.citation.title | Proceedings - 2010 2nd IEEE International Conference on Network Infrastructure and Digital Content, IC-NIDC 2010 | - |
dc.citation.startPage | 944 | - |
dc.citation.endPage | 947 | - |
dc.type.rims | ART | - |
dc.type.docType | Conference Paper | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scopus | - |
dc.subject.keywordPlus | Behavior patterns | - |
dc.subject.keywordPlus | Load-Balancing | - |
dc.subject.keywordPlus | Multi core | - |
dc.subject.keywordPlus | NUMA | - |
dc.subject.keywordPlus | Parallel | - |
dc.subject.keywordPlus | Behavioral research | - |
dc.subject.keywordPlus | Microprocessor chips | - |
dc.subject.keywordPlus | Network architecture | - |
dc.subject.keywordPlus | Parallel architectures | - |
dc.subject.keywordAuthor | Behavior pattern analysis | - |
dc.subject.keywordAuthor | Load balancing | - |
dc.subject.keywordAuthor | Multi-core | - |
dc.subject.keywordAuthor | NUMA | - |
dc.subject.keywordAuthor | Parallel | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/5657935 | - |
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