FULL-WAVE SIMULATION EXAMINING LAYOUT EFFECT IN CMOS RF AMPLIFIER DESIGN

Abstract

procedure which examines the layout effect in a CMOS RE low noise amplifier design based on S-parameters which are extracted using a full-wave simulator HFSS is presented in this article. The S-parameters of the circuit layout are successfully obtained at the bias condition by the proper use of the CMOS active and passive device models, avoiding the nonconvergence problem that exists in the simulator (Liang and Razavi, IEEE J Solid-State Circuits 44 (2009)). The accuracy of the full-wave simulation is verified by determining if the results between the circuit simulation and the simulation with the S-parameters of the ideal connection lines (i.e., DC S-parameters) of the circuit are the same, and its validity is demonstrated via a comparison of the simulated and measured results of a concurrent dual-band LNA operating at 2.4 and 5.2 GHz in 180-nm CMOS technology. (C) 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52:2738-2740, 2010; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.25604