Parallel reconfigurable computing and its application to hidden Markov model
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Paul, Anand | - |
dc.contributor.author | Jiang, , Yung-Chuan | - |
dc.contributor.author | Jeong, Jechang | - |
dc.date.accessioned | 2022-12-20T11:01:31Z | - |
dc.date.available | 2022-12-20T11:01:31Z | - |
dc.date.created | 2022-09-16 | - |
dc.date.issued | 2010-11 | - |
dc.identifier.issn | 0000-0000 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/173442 | - |
dc.description.abstract | Parallel processing techniques are increasingly found in reconfigurable computing, especially in digital signal processing (DSP) applications. In this paper, we design a parallel reconfigurable computing (PRC) architecture which consists of multiple dynamically reconfigurable computing units. The hidden Markov model (HMM) algorithm is mapped onto the PRC architecture. First, we construct a directed acyclic graph (DAG) to represent the HMM algorithms. A novel parallel partition approach is then proposed to map the HMM DAG onto the multiple DRC units in a PRC system. This partitioning algorithm is capable of design optimization of parallel processing reconfigurable systems for a given number of processing elements in different HHM states. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEEE | - |
dc.title | Parallel reconfigurable computing and its application to hidden Markov model | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Jeong, Jechang | - |
dc.identifier.doi | 10.1049/cp.2010.0542 | - |
dc.identifier.scopusid | 2-s2.0-78649616160 | - |
dc.identifier.bibliographicCitation | IET Conference Publications, v.2010, no.568 CP, pp.82 - 91 | - |
dc.relation.isPartOf | IET Conference Publications | - |
dc.citation.title | IET Conference Publications | - |
dc.citation.volume | 2010 | - |
dc.citation.number | 568 CP | - |
dc.citation.startPage | 82 | - |
dc.citation.endPage | 91 | - |
dc.type.rims | ART | - |
dc.type.docType | Conference Paper | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scopus | - |
dc.subject.keywordPlus | FPGA | - |
dc.subject.keywordPlus | HMM | - |
dc.subject.keywordPlus | Parallel processor | - |
dc.subject.keywordPlus | Partitioning algorithms | - |
dc.subject.keywordPlus | Reconfigurable processing | - |
dc.subject.keywordPlus | Algorithms | - |
dc.subject.keywordPlus | Axial flow | - |
dc.subject.keywordPlus | Computation theory | - |
dc.subject.keywordPlus | Hidden Markov models | - |
dc.subject.keywordPlus | Optimization | - |
dc.subject.keywordPlus | Reconfigurable hardware | - |
dc.subject.keywordPlus | Signal processing | - |
dc.subject.keywordPlus | Structural design | - |
dc.subject.keywordPlus | Parallel processing systems | - |
dc.subject.keywordAuthor | FPGA | - |
dc.subject.keywordAuthor | HMM | - |
dc.subject.keywordAuthor | parallel processors | - |
dc.subject.keywordAuthor | partitioning algorithm | - |
dc.subject.keywordAuthor | reconfigurable processing | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/5632286 | - |
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.
222, Wangsimni-ro, Seongdong-gu, Seoul, 04763, Korea+82-2-2220-1365
COPYRIGHT © 2021 HANYANG UNIVERSITY.
Certain data included herein are derived from the © Web of Science of Clarivate Analytics. All rights reserved.
You may not copy or re-distribute this material in whole or in part without the prior written consent of Clarivate Analytics.