Parallel reconfigurable computing and its application to hidden Markov model
- Authors
- Paul, Anand; Jiang, , Yung-Chuan; Jeong, Jechang
- Issue Date
- Nov-2010
- Publisher
- IEEE
- Keywords
- FPGA; HMM; parallel processors; partitioning algorithm; reconfigurable processing
- Citation
- IET Conference Publications, v.2010, no.568 CP, pp.82 - 91
- Indexed
- SCOPUS
- Journal Title
- IET Conference Publications
- Volume
- 2010
- Number
- 568 CP
- Start Page
- 82
- End Page
- 91
- URI
- https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/173442
- DOI
- 10.1049/cp.2010.0542
- ISSN
- 0000-0000
- Abstract
- Parallel processing techniques are increasingly found in reconfigurable computing, especially in digital signal processing (DSP) applications. In this paper, we design a parallel reconfigurable computing (PRC) architecture which consists of multiple dynamically reconfigurable computing units. The hidden Markov model (HMM) algorithm is mapped onto the PRC architecture. First, we construct a directed acyclic graph (DAG) to represent the HMM algorithms. A novel parallel partition approach is then proposed to map the HMM DAG onto the multiple DRC units in a PRC system. This partitioning algorithm is capable of design optimization of parallel processing reconfigurable systems for a given number of processing elements in different HHM states.
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