Improvement of threshold voltage shift distribution characteristic in double layer NiSi2 nanocrystals for nano-floating gate memory applications
- Authors
- Song, Jinho; Park, Junyoup; Kwon, Jihon; Kim, Donghyoun; Song, Wangyu; Choi, Sungjin; Lee, Seung-Beck
- Issue Date
- Aug-2010
- Citation
- 2010 10th IEEE Conference on Nanotechnology, NANO 2010, pp.398 - 401
- Indexed
- SCOPUS
- Journal Title
- 2010 10th IEEE Conference on Nanotechnology, NANO 2010
- Start Page
- 398
- End Page
- 401
- URI
- https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/174304
- DOI
- 10.1109/NANO.2010.5697905
- ISSN
- 0000-0000
- Abstract
- We report on the fabrication and capacitance-voltage characteristics of double layer nickel-silicide nanocrystals with Si3N4 interlayer tunnel barrier for nano-floating gate memory applications. Compared with devices using SiO2 interlayer, the use of Si3N 4 interlayer dielectric reduced the average size (4 nm) and distribution (2.5 nm) of NiSi2 nanocrystal (NC) charge traps by more than 50 % and giving a two fold increase in NC density to 2.3 × 10 12 cm-2. The increased density and reduced NC size distribution resulted in a significantly decrease in the distribution of the device C-V characteristics. For each program voltage, the distribution of the shift in the threshold voltage was reduced by more than 50 % on average to less than 0.7 V, demonstrating possible multi-level-cell operation.
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