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Enhancement of the Programming Speed in SANOS Nonvolatile Memory Device Designed Utilizing Al2O3 and SiO2 Stacked Tunneling Layers
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Kim, Hyun Woo | - |
| dc.contributor.author | Kim, Dong Hun | - |
| dc.contributor.author | You, Joo Hyung | - |
| dc.contributor.author | Kim, Tae Whan | - |
| dc.date.accessioned | 2022-12-20T17:57:34Z | - |
| dc.date.available | 2022-12-20T17:57:34Z | - |
| dc.date.created | 2022-08-27 | - |
| dc.date.issued | 2010-05 | - |
| dc.identifier.issn | 0916-8524 | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/175028 | - |
| dc.description.abstract | The programming characteristics of polysilicon-aluminum oxide-nitride-oxide-silicon (SANOS) nonvolatile memory devices with Al2O3 and SiO2 stacked tunneling layers were investigated. The electron and hole drifts in the Si3N4 layer were calculated to determine the program speed of the proposed SANOS devices. Simulation results showed that enhancement of the programming speed in SANOS was achieved by utilizing SiO2 and Al2O3 stacked tunneling layers. | - |
| dc.language | 영어 | - |
| dc.language.iso | en | - |
| dc.publisher | IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG | - |
| dc.title | Enhancement of the Programming Speed in SANOS Nonvolatile Memory Device Designed Utilizing Al2O3 and SiO2 Stacked Tunneling Layers | - |
| dc.type | Article | - |
| dc.contributor.affiliatedAuthor | Kim, Tae Whan | - |
| dc.identifier.doi | 10.1587/transele.E93.C.651 | - |
| dc.identifier.scopusid | 2-s2.0-77951773828 | - |
| dc.identifier.wosid | 000281341500023 | - |
| dc.identifier.bibliographicCitation | IEICE TRANSACTIONS ON ELECTRONICS, v.E93C, no.5, pp.651 - 653 | - |
| dc.relation.isPartOf | IEICE TRANSACTIONS ON ELECTRONICS | - |
| dc.citation.title | IEICE TRANSACTIONS ON ELECTRONICS | - |
| dc.citation.volume | E93C | - |
| dc.citation.number | 5 | - |
| dc.citation.startPage | 651 | - |
| dc.citation.endPage | 653 | - |
| dc.type.rims | ART | - |
| dc.type.docType | Article | - |
| dc.description.journalClass | 1 | - |
| dc.description.isOpenAccess | N | - |
| dc.description.journalRegisteredClass | scie | - |
| dc.description.journalRegisteredClass | scopus | - |
| dc.relation.journalResearchArea | Engineering | - |
| dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
| dc.subject.keywordPlus | CHARGE-TRANSPORT | - |
| dc.subject.keywordPlus | NITRIDE | - |
| dc.subject.keywordPlus | SONOS | - |
| dc.subject.keywordAuthor | SANOS | - |
| dc.subject.keywordAuthor | SONOS | - |
| dc.subject.keywordAuthor | charge transport | - |
| dc.subject.keywordAuthor | silicon nitride | - |
| dc.subject.keywordAuthor | stacked tunneling layer | - |
| dc.identifier.url | https://www.jstage.jst.go.jp/article/transele/E93.C/5/E93.C_5_651/_article | - |
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