CMOS MULTI-BAND WIRELESS DIRECT-CONVERSION RECEIVER FOR SDR
- Authors
- Lee, Sangho; Choi, Sanghyun; Lee, Jaeseok; Park, Jihyun; Kim, Hyeongdong
- Issue Date
- Mar-2010
- Publisher
- John Wiley & Sons Inc.
- Keywords
- RF CMOS; multi-band; receiver; sub-harmonic
- Citation
- Microwave and Optical Technology Letters, v.52, no.3, pp 718 - 721
- Pages
- 4
- Indexed
- SCIE
SCOPUS
- Journal Title
- Microwave and Optical Technology Letters
- Volume
- 52
- Number
- 3
- Start Page
- 718
- End Page
- 721
- URI
- https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/175326
- DOI
- 10.1002/mop.24989
- ISSN
- 0895-2477
1098-2760
- Abstract
- In this article, a CMOS multistandard wireless direct-conversion receiver is designed. The receiver is composed of three components low noise amplifier, voltage-controlled oscillator, and mixer. In details, the designed receiver adopts direct-conversion architecture and accomodates three standards WCDMA, Wibro (or mobile WIMAX), and CDMA 2000 lx 184-24 GHz the designed mixer is a passive subharmonic doubly balanced structure, the VCO is a back-gate coupling quadrature VCO, and the LNA is a differential structure. Each component is designed with relevance to direct-conversion architecture. The designed mixer has no flicker noise theoretically because the mixing transistors operate in the triode region. Also, DC offset problem is avoided, because local oscillation frequency is half of RF frequency and the port isolation is improved by the innate characteristic of a balanced structure. The VCO generates a quadrature signal and the oscillation frequency is half of RF frequency to drive designed sub-harmonic mixer. No coupling transistors are needed due to the use of back-gate coupling to reduce flicker noise. back-gate coupling means that the body of a transistor is used as another gate. The LNA, which adopts a well-known cascade structure, is designed as a differential structure to suppress common mode noise and to drive a doubly balanced mixer. All designed components are fabricated by the TSMC 0 18-mu m RF CMOS process.
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