Nanoscale Two-bit/cell NAND Silicon-oxide-nitride-oxide-silicon Flash Memories with an Advanced Saddle Structure
- Authors
- Park, Sang Su; Oh, Se Woong; Dal Kwack, Kae; Kim, Tae Whan; Kim, Hyun Joo
- Issue Date
- Jul-2009
- Publisher
- 한국물리학회
- Keywords
- Saddle structure; NAND SONOS flash memory; Two-bit/cell; Charge density; Scaling down
- Citation
- Journal of the Korean Physical Society, v.55, no.1, pp 236 - 240
- Pages
- 5
- Indexed
- SCIE
SCOPUS
KCI
- Journal Title
- Journal of the Korean Physical Society
- Volume
- 55
- Number
- 1
- Start Page
- 236
- End Page
- 240
- URI
- https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/176538
- DOI
- 10.3938/jkps.55.236
- ISSN
- 0374-4884
1976-8524
- Abstract
- Nanoscale two-bit/cell three-dimensional NAND silicon-oxide-nitride-oxide-silicon (SONOS) flash memories with an advanced saddle structure separated from the tunneling oxide-charge trap layer-blocking oxide were designed to increase the storage density of the memory devices and to remove the short channel and narrow width effects. The narrow charge distribution of the trap charge in the two-bit/cell SONOS memories was achieved due to the structural separation of the charge trap layer. The program and the erase efficiencies were simulated by using technology computer-aided design tools. The program and the erase characteristics of the Fowler-Nordheim tunneling processes were estimated to verify the unique two-bit/cell SONOS memories. The memory density and the operating speed of the proposed nanoscale two-bit/cell NAND SONOS memories were larger.
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