Fabrication of n-type Schottky barrier thin-film transistor with channel length and width of 0.1 mu m and erbium silicide source/drain

Abstract

In this paper, a Schottky barrier polycrystalline silicon thin-film transistor (SB TFT) with erbium silicide source/drain is demonstrated using low temperature processes. A low temperature oxide is used for a gate dielectric and the transistor channel is crystallized by a metal-induced lateral crystallization process. An n-type SB TFT shows a normal electrical performance with subthreshold slope of 239 mV/dec, I-ON/I-OFF ratio of 5.8 x 10(4) and I-ON of 2 mu A/mu m at V-G=3 V, V-D = 2.5 V for 0.1 mu m device. A process temperature is maintained at less than 600 degrees C throughout the whole processes. The SB TFT is expected to be a promising candidate for a next system-on-glass technology and an alternative 3D integration technology.