Dependence of memory margin of Cap-less memory cells on top Si thickness

Abstract

We investigated the dependence of Cap-less memory on top of silicon with a thickness between 15.5 and 72.3 nm. It was confirmed that the memory margin depends on the impact ionization rate associated with the increased conduction current density and the decreased lateral electric field as the top silicon thickness increases. In particular, we observed that the maximum memory margin is 61 mu A at a 45 nm top silicon thickness, where the impact ionization rate is maximized. Consequently, we obtained the optimal top silicon thickness of 45 nm for Cap-less memory cells operating in fully depleted silicon-on-insulator n-metal-oxide-semiconductor field-effect transistors.