The impact of wafer nanotopography on threshold voltage variation in NAND flash memory cells fabricated with poly-silicon chemical mechanical polishing

Abstract

Based on simulation, the threshold voltage (VT) variation for NAND flash memory cells fabricated with the self-alignment of the poly-silicon floating gate is expected to be related to the peak-to-valley value (PV) of wafer nanotopography. After chemical and mechanical polishing (CMP) of the poly-silicon floating gate, the PV of the remaining height of the poly-silicon floating gate linearly increased with the PV of wafer nanotopography. As a result, the VT variation linearly increased with the PV of the remaining height of the poly-silicon floating gate after CMP. These simulation results show, in particular, that the VT variation of NAND flash memory cells induced by wafer nanotopography becomes larger and larger as the device size becomes smaller and smaller.