LRU-WSR: Integration of LRU and writes sequence reordering for flash memory
- Authors
- Jung, Hoyoung; Shim, Hyoki; Park, Sungmin; Kang, Sooyong; Cha, Jaehyuk
- Issue Date
- Aug-2008
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- flash memory; buffer replacement; storage system
- Citation
- IEEE TRANSACTIONS ON CONSUMER ELECTRONICS, v.54, no.3, pp.1215 - 1223
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE TRANSACTIONS ON CONSUMER ELECTRONICS
- Volume
- 54
- Number
- 3
- Start Page
- 1215
- End Page
- 1223
- URI
- https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/178102
- DOI
- 10.1109/TCE.2008.4637609
- ISSN
- 0098-3063
- Abstract
- Most mobile devices are equipped with a NAND flash memory even if it has characteristics of not-in-place update and asymmetric I/O latencies among read, write, and erase operations: write/erase operations are much slower than a read operation in a flash memory. For the overall performance of a flash memory system, the buffer replacement policy should consider the above severely asymmetric I/O latencies. However, existing LRU buffer replacement algorithm cannot deal with the above problem. This paper proposes the LRU-WSR buffer replacement algorithm that enhances LRU by reordering writes of not-cold dirty pages from the buffer cache to flash storage. The enhanced LRU- WSR algorithm focuses on reducing the number of write/erase operations as well as preventing serious degradation of buffer hit ratio. The experimental results show that the LRU-WSR outperforms other algorithms including LRU, CF-LRU, and FAB(1).
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