Three-dimensional simulation of dopant-fluctuation-induced threshold voltage dispersion in nonplanar MOS structures targeting flash EEPROM transistors

Abstract

Threshold voltage (VT) dispersion due to random discrete dopant fluctuation was simulated in recessed-channel, triple-gate, and saddle MOS structures, targeting future floating-gate memory cell transistor. All nonplanar structures showed improved VT dispersion characteristics, compared with the planar type by proper adjustment of the tunnel oxide structure and channel doping level. The recessed-channel showed a continuous improvement of VT dispersion with the channel area widening beyond a certain threshold recess depth. In triple-gate structure, a significant reduction in VT dispersion is shown possible primarily via the superior gate controllability. Among the nonplanar structures, the saddle structure yielded the lowest VT variation for a fixed target VT with the choice of moderate device parameters from the other structures.