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A design of the signal processing hardware platform for communication systems

Authors
Lee, Byung WookCho, Sung Ho
Issue Date
Mar-2008
Publisher
Oxford University Press
Keywords
OFDM; IEEE 802.16; FPGA; DSP platform
Citation
IEICE Transactions on Communications, v.E91B, no.3, pp 939 - 942
Pages
4
Indexed
SCIE
SCOPUS
Journal Title
IEICE Transactions on Communications
Volume
E91B
Number
3
Start Page
939
End Page
942
URI
https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/178912
DOI
10.1093/ietcom/e91-b.3.939
ISSN
0916-8516
1745-1345
Abstract
In this letter, an efficient hardware platform for the digital signal processing for OFDM communication systems is presented. The hardware platform consists of a single FPGA having 900 K gates, two DSPs with maximum 8,000 MIPS at 1 GHz clock, 2-channel ADC and DAC supporting maximum 125 MHz sampling rate, and flexible data bus architecture, so that a wide variety of baseband signal processing algorithms for practical OFDM communication systems may be implemented and tested. The IEEE 802.16d software modem is also presented in order to verify the effectiveness and usefulness of the designed platform.
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