LIRS-WSR: Integration of LIRS and Writes Sequence Reordering for flash memory
- Authors
- Jung, Hoyoung; Yoon, Kyunghoon; Shim, Hyoki; Park, Sungmin; Kang, Sooyong; Cha, Jae Hyuk
- Issue Date
- Aug-2007
- Publisher
- Springer Verlag
- Keywords
- Buffer replacement algorithm; Embedded system; Flash memory; Storage system
- Citation
- Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), v.4705 LNCS, no.PART 1, pp.224 - 237
- Indexed
- SCOPUS
- Journal Title
- Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
- Volume
- 4705 LNCS
- Number
- PART 1
- Start Page
- 224
- End Page
- 237
- URI
- https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/179745
- DOI
- 10.1007/978-3-540-74472-6_18
- ISSN
- 0302-9743
- Abstract
- Most of the mobile devices are equipped with NAND flash memories even if it has characteristics of not-in-place update and asymmetric I/O latencies among read, write, and erase operations: a write/erase operation is much slower than a read operation in a flash memory. For the overall performance of a flash memory system, the buffer replacement policy should consider the above severely asymmetric I/O latencies. Existing buffer replacement algorithms such as LRU, LIRS, and ARC cannot deal with the above problems. This paper proposes an add-on buffer replacement policy that enhances LIRS by reordering writes of not-cold dirty pages from the buffer cache to flash storage. The enhances LIRS-WSR algorithm focuses on reducing the number of write/erase operations as well as preventing serious degradation of buffer hit ratio. The trace-driven simulation results show that, among the existing buffer replacement algorithms including LRU, CF-LRU, ARC, and LIRS, our LIRSWSR is best in almost cases for flash storage systems.
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