SONA: An on-chip network for scalable interconnection of AMBA-based IPs
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Jung, Eui Bong | - |
dc.contributor.author | Cho, Han Wook | - |
dc.contributor.author | Park, Neungsoo | - |
dc.contributor.author | Song, Yong Ho | - |
dc.date.accessioned | 2022-12-21T11:35:32Z | - |
dc.date.available | 2022-12-21T11:35:32Z | - |
dc.date.created | 2022-08-26 | - |
dc.date.issued | 2006-05 | - |
dc.identifier.issn | 0302-9743 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/181535 | - |
dc.description.abstract | Many recent SoCs use one or more busses to provide internal communication paths among integrated IP cores. As the number of cores in a SoC increases, however, the non-scalable communication bandwidth of bus tends to become a bottleneck to achieve high performance. In this paper, we present a scalable switch-based on-chip network, called SONA, which can be used to provide communication paths among existing AMBA-based IP cores. The network interfaces and routers for the on-chip network are modeled in register transfer level and simulated to measure the performance in latency. The simulation results indicate that the proposed on-chip network can be used to provide scalable communication infrastructure for AMBA-based IP cores with a reasonable cost. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | SPRINGER-VERLAG BERLIN | - |
dc.title | SONA: An on-chip network for scalable interconnection of AMBA-based IPs | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Song, Yong Ho | - |
dc.identifier.doi | 10.1007/11758549_37 | - |
dc.identifier.scopusid | 2-s2.0-33746613653 | - |
dc.identifier.wosid | 000238417500037 | - |
dc.identifier.bibliographicCitation | COMPUTATIONAL SCIENCE - ICCS 2006, PT 4, PROCEEDINGS, v.3994, pp.244 - 251 | - |
dc.relation.isPartOf | COMPUTATIONAL SCIENCE - ICCS 2006, PT 4, PROCEEDINGS | - |
dc.citation.title | COMPUTATIONAL SCIENCE - ICCS 2006, PT 4, PROCEEDINGS | - |
dc.citation.volume | 3994 | - |
dc.citation.startPage | 244 | - |
dc.citation.endPage | 251 | - |
dc.type.rims | ART | - |
dc.type.docType | Article; Proceedings Paper | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Theory & Methods | - |
dc.subject.keywordPlus | Communication channels (information theory) | - |
dc.subject.keywordPlus | Computer simulation | - |
dc.subject.keywordPlus | Interfaces (computer) | - |
dc.subject.keywordPlus | Internet | - |
dc.subject.keywordPlus | Microprocessor chips | - |
dc.subject.keywordPlus | Network protocols | - |
dc.identifier.url | https://link.springer.com/chapter/10.1007/11758549_37 | - |
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