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An Analysis of CMOS Latched Comparators

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dc.contributor.authorYeom, Sunoh-
dc.contributor.author심태양-
dc.contributor.authorHan, Jaeduk-
dc.date.accessioned2023-05-03T09:40:45Z-
dc.date.available2023-05-03T09:40:45Z-
dc.date.issued2023-02-
dc.identifier.urihttps://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/184857-
dc.description.abstractUsing suitable types of CMOS latched comparators for specific conditions is vital -because each comparator has different pros and cons. Also, it is important to determine which comparators to utilize for specific conditions. A need remains for the practical comparison of various types of comparators with applicable criteria. Within the present study, we performed comparisons between StrongArm latch, modified double-tail latch, and track-and-regenerate slicer with three different types of criteria. We analyzed each comparator by controlling three types of variables: power supply, input common mode voltage, and differential signal input. Then, in keeping with these three types of criteria, the simulation results, kickback noise, power consumption, and clock-to-Q delay were evaluated. We designed three kinds of CMOS latched comparators with 40-nm CMOS technology. In post-layout simulations, using a StrongArm latch resulted in low power consumption. Modified double-tail latch showed strength in kickback noise and is applicable for low power supply. Track-and-regenerate slicer showed better performance in clock-to-Q delay. Our findings expand on the performance of each comparator that would be applied to mixed-signal circuits and systems.-
dc.format.extent4-
dc.language영어-
dc.language.isoENG-
dc.publisherInstitute of Electrical and Electronics Engineers Inc.-
dc.titleAn Analysis of CMOS Latched Comparators-
dc.typeArticle-
dc.publisher.location미국-
dc.identifier.doi10.1109/ICEIC57457.2023.10049873-
dc.identifier.scopusid2-s2.0-85150421375-
dc.identifier.bibliographicCitation2023 International Conference on Electronics, Information, and Communication, ICEIC 2023, pp 1 - 4-
dc.citation.title2023 International Conference on Electronics, Information, and Communication, ICEIC 2023-
dc.citation.startPage1-
dc.citation.endPage4-
dc.type.docTypeConference Paper-
dc.description.isOpenAccessN-
dc.description.journalRegisteredClassscopus-
dc.subject.keywordPlusClocks-
dc.subject.keywordPlusCMOS integrated circuits-
dc.subject.keywordPlusComparator circuits-
dc.subject.keywordPlusElectric power utilization-
dc.subject.keywordPlusElectric signal systems-
dc.subject.keywordPlusMixed signal integrated circuits-
dc.subject.keywordPlusComparators (optical)-
dc.subject.keywordPlusClock-to-Q delay-
dc.subject.keywordPlusCMOS-
dc.subject.keywordPlusCondition-
dc.subject.keywordPlusKickback noise-
dc.subject.keywordPlusLatched comparator-
dc.subject.keywordPlusPerformance-
dc.subject.keywordPlusPower supply-
dc.subject.keywordPlusSlice-
dc.subject.keywordPlusStrongARM-
dc.subject.keywordPlusVariable power-
dc.subject.keywordAuthorclock-to-Q delay-
dc.subject.keywordAuthorCMOS-
dc.subject.keywordAuthorkickback noise-
dc.subject.keywordAuthorlatched comparator-
dc.subject.keywordAuthorslicer-
dc.identifier.urlhttps://ieeexplore.ieee.org/document/10049873-
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