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An Analysis of CMOS Latched Comparators
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Yeom, Sunoh | - |
| dc.contributor.author | 심태양 | - |
| dc.contributor.author | Han, Jaeduk | - |
| dc.date.accessioned | 2023-05-03T09:40:45Z | - |
| dc.date.available | 2023-05-03T09:40:45Z | - |
| dc.date.issued | 2023-02 | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/184857 | - |
| dc.description.abstract | Using suitable types of CMOS latched comparators for specific conditions is vital -because each comparator has different pros and cons. Also, it is important to determine which comparators to utilize for specific conditions. A need remains for the practical comparison of various types of comparators with applicable criteria. Within the present study, we performed comparisons between StrongArm latch, modified double-tail latch, and track-and-regenerate slicer with three different types of criteria. We analyzed each comparator by controlling three types of variables: power supply, input common mode voltage, and differential signal input. Then, in keeping with these three types of criteria, the simulation results, kickback noise, power consumption, and clock-to-Q delay were evaluated. We designed three kinds of CMOS latched comparators with 40-nm CMOS technology. In post-layout simulations, using a StrongArm latch resulted in low power consumption. Modified double-tail latch showed strength in kickback noise and is applicable for low power supply. Track-and-regenerate slicer showed better performance in clock-to-Q delay. Our findings expand on the performance of each comparator that would be applied to mixed-signal circuits and systems. | - |
| dc.format.extent | 4 | - |
| dc.language | 영어 | - |
| dc.language.iso | ENG | - |
| dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
| dc.title | An Analysis of CMOS Latched Comparators | - |
| dc.type | Article | - |
| dc.publisher.location | 미국 | - |
| dc.identifier.doi | 10.1109/ICEIC57457.2023.10049873 | - |
| dc.identifier.scopusid | 2-s2.0-85150421375 | - |
| dc.identifier.bibliographicCitation | 2023 International Conference on Electronics, Information, and Communication, ICEIC 2023, pp 1 - 4 | - |
| dc.citation.title | 2023 International Conference on Electronics, Information, and Communication, ICEIC 2023 | - |
| dc.citation.startPage | 1 | - |
| dc.citation.endPage | 4 | - |
| dc.type.docType | Conference Paper | - |
| dc.description.isOpenAccess | N | - |
| dc.description.journalRegisteredClass | scopus | - |
| dc.subject.keywordPlus | Clocks | - |
| dc.subject.keywordPlus | CMOS integrated circuits | - |
| dc.subject.keywordPlus | Comparator circuits | - |
| dc.subject.keywordPlus | Electric power utilization | - |
| dc.subject.keywordPlus | Electric signal systems | - |
| dc.subject.keywordPlus | Mixed signal integrated circuits | - |
| dc.subject.keywordPlus | Comparators (optical) | - |
| dc.subject.keywordPlus | Clock-to-Q delay | - |
| dc.subject.keywordPlus | CMOS | - |
| dc.subject.keywordPlus | Condition | - |
| dc.subject.keywordPlus | Kickback noise | - |
| dc.subject.keywordPlus | Latched comparator | - |
| dc.subject.keywordPlus | Performance | - |
| dc.subject.keywordPlus | Power supply | - |
| dc.subject.keywordPlus | Slice | - |
| dc.subject.keywordPlus | StrongARM | - |
| dc.subject.keywordPlus | Variable power | - |
| dc.subject.keywordAuthor | clock-to-Q delay | - |
| dc.subject.keywordAuthor | CMOS | - |
| dc.subject.keywordAuthor | kickback noise | - |
| dc.subject.keywordAuthor | latched comparator | - |
| dc.subject.keywordAuthor | slicer | - |
| dc.identifier.url | https://ieeexplore.ieee.org/document/10049873 | - |
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