Threshold Voltage Shift Variation of Vertical NAND Flash Memory Devices Dependent on Polysilicon Channel Layer Thickness

Abstract

The threshold voltage shift variations of vertical NAND flash memory devices dependent on polysilicon channel layer thickness were investigated. The threshold voltage shift of the target cell for vertical NAND flash memory devices was improved with decreasing polysilicon channel layer. The program/erase characteristics of vertical NAND flash memory devices such as the tunneling oxide electric field and program efficiency are affected by variation of the polysilicon channel layer thickness. The critical thickness of the polysilicon channel layer was 2 nm where the difference between the threshold voltage shift with and without the quantum effect was lower than 0.4 V. The cell interference in vertical NAND flash memory devices with a cell length of 15 nm and a cell-to-cell distance of 15 nm was significantly affected by variation of the polysilicon channel layer thickness. Among the differences in the threshold voltage shifts between the programmed target cell and the adjacent cell below 0.5 V, a 4 nm thickness of the polysilicon channel layer for vertical NAND flash memory devices was the optimal value.