Performance Evaluation of Strain Effectiveness of Sub-5 nm GAA FETs with Compact Modeling based on Neural Networks

Abstract

In this paper, strain effectiveness in 3-stacked gate-all-around (GAA) FETs has been investigated using process and device simulations for sub-5 nm technology node. We induce strain into the Si channels in GAA FETs by modifying the source and drain epitaxy to investigate the effectiveness of strain in GAA FETs. We chose SiGe as source and drain for pMOS, and SiC for nMOS. To verify I-V characteristics of GAA FETs, the drift-diffusion transport model was calibrated with Monte Carlo simulations. Furthermore, a compact model based on neural networks has been developed to evaluate the performance of a 5-stage ring oscillator with strained and unstrained GAA FETs using SPICE simulation. Our simulation results indicate that circuits with 1 % strained GAA FETs shows 92.22 ps ring oscillator propagation delay time compared to 130.67 ps with unstrained GAA FETs © 2023 IEEE.