Thermally Activated Defect Engineering for Highly Stable and Uniform ALD-Amorphous IGZO TFTs with High-Temperature Compatibility
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Dong-Gyu | - |
dc.contributor.author | Lee, Won-Bum | - |
dc.contributor.author | Lee, Seunghee | - |
dc.contributor.author | Koh, Jihyun | - |
dc.contributor.author | Kuh, Bongjin | - |
dc.contributor.author | Park, Jin-Seong | - |
dc.date.accessioned | 2023-08-22T03:01:27Z | - |
dc.date.available | 2023-08-22T03:01:27Z | - |
dc.date.created | 2023-08-17 | - |
dc.date.issued | 2023-07 | - |
dc.identifier.issn | 1944-8244 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/189427 | - |
dc.description.abstract | Highly stable IGZO thin-film transistors derived fromatomic layerdeposition are crucial for the semiconductor industry. However, unavoidabledefect generation during high-temperature annealing results in abnormalpositive bias temperature stress (PBTS). Herein, we propose a defectengineering method by controlling the gate insulator (GI) depositiontemperature. Applying a GI deposition temperature of 400 & DEG;C tothe In0.52Ga0.18Zn0.30O active layereffectively suppresses defects even after 600 & DEG;C annealing, preservingthe amorphous phase of IGZO. The device exhibits a threshold voltage(V (TH)) of 0.05 V, a field-effect mobilityof 27.6 cm(2)/Vs, a subthreshold swing of 61 mV/decade, anda hysteresis voltage of 0.01 V, demonstrating highly reliable PBTSand negative bias temperature stress. A power-law fit of the PBTSstability under 2 MV/cm of gate field stress and 120 & DEG;C of temperaturestress predicts a V (TH) shift of -0.01V after 10 years. Moreover, the proposed method ensures reliable uniformityover a large 4 in. area. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | AMER CHEMICAL SOC | - |
dc.title | Thermally Activated Defect Engineering for Highly Stable and Uniform ALD-Amorphous IGZO TFTs with High-Temperature Compatibility | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Park, Jin-Seong | - |
dc.identifier.doi | 10.1021/acsami.3c06517 | - |
dc.identifier.scopusid | 2-s2.0-85166442282 | - |
dc.identifier.wosid | 001033278200001 | - |
dc.identifier.bibliographicCitation | ACS APPLIED MATERIALS & INTERFACES, v.15, no.30, pp.36550 - 36563 | - |
dc.relation.isPartOf | ACS APPLIED MATERIALS & INTERFACES | - |
dc.citation.title | ACS APPLIED MATERIALS & INTERFACES | - |
dc.citation.volume | 15 | - |
dc.citation.number | 30 | - |
dc.citation.startPage | 36550 | - |
dc.citation.endPage | 36563 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Science & Technology - Other Topics | - |
dc.relation.journalResearchArea | Materials Science | - |
dc.relation.journalWebOfScienceCategory | Nanoscience & Nanotechnology | - |
dc.relation.journalWebOfScienceCategory | Materials Science, Multidisciplinary | - |
dc.subject.keywordPlus | THIN-FILM TRANSISTORS | - |
dc.subject.keywordPlus | ATOMIC LAYER DEPOSITION | - |
dc.subject.keywordPlus | DIELECTRIC-BREAKDOWN | - |
dc.subject.keywordAuthor | atomic layer deposition (ALD) | - |
dc.subject.keywordAuthor | IGZO | - |
dc.subject.keywordAuthor | thin-filmtransistor (TFT) | - |
dc.subject.keywordAuthor | Al2O3 | - |
dc.subject.keywordAuthor | gateinsulator | - |
dc.subject.keywordAuthor | deposition temperature | - |
dc.subject.keywordAuthor | positive biastemperature stress (PBTS) | - |
dc.identifier.url | https://pubs.acs.org/doi/10.1021/acsami.3c06517 | - |
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