Thermally Activated Defect Engineering for Highly Stable and Uniform ALD-Amorphous IGZO TFTs with High-Temperature Compatibility

Abstract

Highly stable IGZO thin-film transistors derived fromatomic layerdeposition are crucial for the semiconductor industry. However, unavoidabledefect generation during high-temperature annealing results in abnormalpositive bias temperature stress (PBTS). Herein, we propose a defectengineering method by controlling the gate insulator (GI) depositiontemperature. Applying a GI deposition temperature of 400 & DEG;C tothe In0.52Ga0.18Zn0.30O active layereffectively suppresses defects even after 600 & DEG;C annealing, preservingthe amorphous phase of IGZO. The device exhibits a threshold voltage(V (TH)) of 0.05 V, a field-effect mobilityof 27.6 cm(2)/Vs, a subthreshold swing of 61 mV/decade, anda hysteresis voltage of 0.01 V, demonstrating highly reliable PBTSand negative bias temperature stress. A power-law fit of the PBTSstability under 2 MV/cm of gate field stress and 120 & DEG;C of temperaturestress predicts a V (TH) shift of -0.01V after 10 years. Moreover, the proposed method ensures reliable uniformityover a large 4 in. area.