Anomalously Beneficial Gate-Length Scaling Trend of Negative Capacitance Transistors
DC Field | Value | Language |
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dc.contributor.author | Liao, Yu-Hung | - |
dc.contributor.author | Kwon, Daewoong | - |
dc.contributor.author | Lin, Yen-Kai | - |
dc.contributor.author | Tan, Ava Jiang | - |
dc.contributor.author | Hu, Chenming | - |
dc.contributor.author | Salahuddin, Sayeef | - |
dc.date.accessioned | 2023-09-04T07:43:20Z | - |
dc.date.available | 2023-09-04T07:43:20Z | - |
dc.date.created | 2023-07-21 | - |
dc.date.issued | 2019-11 | - |
dc.identifier.issn | 0741-3106 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/189909 | - |
dc.description.abstract | The Negative Capacitance Field Effect Transistors exhibit excellent SS and DIBL improvements from the control MOSFET devices at very short gate lengths, a phenomenon which cannot be explained using conventional MOSFET theory. This benefit arises from an effect which acts similarly to decreasing the equivalent-oxide thickness at short gate lengths. The effect is observed in both TCAD simulations and experiments, and is explained by the conjunction of the source/drain inner fringing field and the nonlinear polarizability of ferroelectric materials. The results present a sharp contrast to conventional scaling theory and bode well for extending the MOSFET gate length scaling limit. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | Anomalously Beneficial Gate-Length Scaling Trend of Negative Capacitance Transistors | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Kwon, Daewoong | - |
dc.identifier.doi | 10.1109/LED.2019.2940715 | - |
dc.identifier.scopusid | 2-s2.0-85074533318 | - |
dc.identifier.wosid | 000496192600039 | - |
dc.identifier.bibliographicCitation | IEEE ELECTRON DEVICE LETTERS, v.40, no.11, pp.1860 - 1863 | - |
dc.relation.isPartOf | IEEE ELECTRON DEVICE LETTERS | - |
dc.citation.title | IEEE ELECTRON DEVICE LETTERS | - |
dc.citation.volume | 40 | - |
dc.citation.number | 11 | - |
dc.citation.startPage | 1860 | - |
dc.citation.endPage | 1863 | - |
dc.type.rims | ART | - |
dc.type.docType | 정기 학술지(letter(letters to the editor)) | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | FET | - |
dc.subject.keywordAuthor | Logic gates | - |
dc.subject.keywordAuthor | Capacitance | - |
dc.subject.keywordAuthor | Iron | - |
dc.subject.keywordAuthor | Market research | - |
dc.subject.keywordAuthor | MOSFET | - |
dc.subject.keywordAuthor | Ferroelectric materials | - |
dc.subject.keywordAuthor | Negative capacitance | - |
dc.subject.keywordAuthor | ferroelectric | - |
dc.subject.keywordAuthor | short channel effects | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/8835063 | - |
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