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Anomalously Beneficial Gate-Length Scaling Trend of Negative Capacitance Transistors

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dc.contributor.authorLiao, Yu-Hung-
dc.contributor.authorKwon, Daewoong-
dc.contributor.authorLin, Yen-Kai-
dc.contributor.authorTan, Ava Jiang-
dc.contributor.authorHu, Chenming-
dc.contributor.authorSalahuddin, Sayeef-
dc.date.accessioned2023-09-04T07:43:20Z-
dc.date.available2023-09-04T07:43:20Z-
dc.date.created2023-07-21-
dc.date.issued2019-11-
dc.identifier.issn0741-3106-
dc.identifier.urihttps://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/189909-
dc.description.abstractThe Negative Capacitance Field Effect Transistors exhibit excellent SS and DIBL improvements from the control MOSFET devices at very short gate lengths, a phenomenon which cannot be explained using conventional MOSFET theory. This benefit arises from an effect which acts similarly to decreasing the equivalent-oxide thickness at short gate lengths. The effect is observed in both TCAD simulations and experiments, and is explained by the conjunction of the source/drain inner fringing field and the nonlinear polarizability of ferroelectric materials. The results present a sharp contrast to conventional scaling theory and bode well for extending the MOSFET gate length scaling limit.-
dc.language영어-
dc.language.isoen-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.titleAnomalously Beneficial Gate-Length Scaling Trend of Negative Capacitance Transistors-
dc.typeArticle-
dc.contributor.affiliatedAuthorKwon, Daewoong-
dc.identifier.doi10.1109/LED.2019.2940715-
dc.identifier.scopusid2-s2.0-85074533318-
dc.identifier.wosid000496192600039-
dc.identifier.bibliographicCitationIEEE ELECTRON DEVICE LETTERS, v.40, no.11, pp.1860 - 1863-
dc.relation.isPartOfIEEE ELECTRON DEVICE LETTERS-
dc.citation.titleIEEE ELECTRON DEVICE LETTERS-
dc.citation.volume40-
dc.citation.number11-
dc.citation.startPage1860-
dc.citation.endPage1863-
dc.type.rimsART-
dc.type.docType정기 학술지(letter(letters to the editor))-
dc.description.journalClass1-
dc.description.isOpenAccessN-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.subject.keywordPlusFET-
dc.subject.keywordAuthorLogic gates-
dc.subject.keywordAuthorCapacitance-
dc.subject.keywordAuthorIron-
dc.subject.keywordAuthorMarket research-
dc.subject.keywordAuthorMOSFET-
dc.subject.keywordAuthorFerroelectric materials-
dc.subject.keywordAuthorNegative capacitance-
dc.subject.keywordAuthorferroelectric-
dc.subject.keywordAuthorshort channel effects-
dc.identifier.urlhttps://ieeexplore.ieee.org/document/8835063-
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