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Challenges to Partial Switching of Hf0.8Zr0.2O2 Gated Ferroelectric FET for Multilevel/Analog or Low-voltage Memory Operation

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dc.contributor.authorChatterjee, Korok-
dc.contributor.authorKim, Sangwan-
dc.contributor.authorKarbasian, Golnaz-
dc.contributor.authorKwon, Daewoong-
dc.contributor.authorTan, Ava J.-
dc.contributor.authorYadav, Ajay K.-
dc.contributor.authorSerrao, Claudy R.-
dc.contributor.authorHu, Chenming-
dc.contributor.authorSalahuddin, Sayeef-
dc.date.accessioned2023-09-04T07:43:38Z-
dc.date.available2023-09-04T07:43:38Z-
dc.date.created2023-07-21-
dc.date.issued2019-09-
dc.identifier.issn0741-3106-
dc.identifier.urihttps://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/189911-
dc.description.abstractThe ability to partially switch an FeFET could enable their use as an embedded low-voltage memory and as analog weight storage in artificial neural networks (ANNs). We report on memory characterization of FeFETs gated with 5.5-nm Hf0.8Zr0.2O2, fabricated on fully depleted silicon-on-insulator using a self-aligned, gate last process. We find that for a single device, excellent elevated temperature retention, program/erase endurance, and read endurance are obtained; however, there is significant device to device variability in the response of the ferroelectric to a partially switching program pulse, which may require the use of feedback in programming.-
dc.language영어-
dc.language.isoen-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.titleChallenges to Partial Switching of Hf0.8Zr0.2O2 Gated Ferroelectric FET for Multilevel/Analog or Low-voltage Memory Operation-
dc.typeArticle-
dc.contributor.affiliatedAuthorKwon, Daewoong-
dc.identifier.doi10.1109/LED.2019.2931430-
dc.identifier.scopusid2-s2.0-85089476081-
dc.identifier.wosid000483014600020-
dc.identifier.bibliographicCitationIEEE ELECTRON DEVICE LETTERS, v.40, no.9, pp.1423 - 1426-
dc.relation.isPartOfIEEE ELECTRON DEVICE LETTERS-
dc.citation.titleIEEE ELECTRON DEVICE LETTERS-
dc.citation.volume40-
dc.citation.number9-
dc.citation.startPage1423-
dc.citation.endPage1426-
dc.type.rimsART-
dc.type.docType정기 학술지(letter(letters to the editor))-
dc.description.journalClass1-
dc.description.isOpenAccessN-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.subject.keywordPlusElevated temperature-
dc.subject.keywordPlusFully depleted silicon-on-insulator-
dc.subject.keywordPlusGate-last process-
dc.subject.keywordPlusLow voltages-
dc.subject.keywordPlusMemory operations-
dc.subject.keywordPlusProgram/erase-
dc.subject.keywordPlusSelf-aligned-
dc.subject.keywordPlusSwitching program-
dc.subject.keywordAuthorFerroelectric-
dc.subject.keywordAuthorhafnium zirconium oxide-
dc.subject.keywordAuthormemory-
dc.subject.keywordAuthorgate last-
dc.subject.keywordAuthorsilicon-on-insulator-
dc.subject.keywordAuthorneuromorphic computing-
dc.subject.keywordAuthordeep learning-
dc.subject.keywordAuthorartificial intelligence-
dc.identifier.urlhttps://ieeexplore.ieee.org/document/8777131-
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