Challenges to Partial Switching of Hf0.8Zr0.2O2 Gated Ferroelectric FET for Multilevel/Analog or Low-voltage Memory Operation
DC Field | Value | Language |
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dc.contributor.author | Chatterjee, Korok | - |
dc.contributor.author | Kim, Sangwan | - |
dc.contributor.author | Karbasian, Golnaz | - |
dc.contributor.author | Kwon, Daewoong | - |
dc.contributor.author | Tan, Ava J. | - |
dc.contributor.author | Yadav, Ajay K. | - |
dc.contributor.author | Serrao, Claudy R. | - |
dc.contributor.author | Hu, Chenming | - |
dc.contributor.author | Salahuddin, Sayeef | - |
dc.date.accessioned | 2023-09-04T07:43:38Z | - |
dc.date.available | 2023-09-04T07:43:38Z | - |
dc.date.created | 2023-07-21 | - |
dc.date.issued | 2019-09 | - |
dc.identifier.issn | 0741-3106 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/189911 | - |
dc.description.abstract | The ability to partially switch an FeFET could enable their use as an embedded low-voltage memory and as analog weight storage in artificial neural networks (ANNs). We report on memory characterization of FeFETs gated with 5.5-nm Hf0.8Zr0.2O2, fabricated on fully depleted silicon-on-insulator using a self-aligned, gate last process. We find that for a single device, excellent elevated temperature retention, program/erase endurance, and read endurance are obtained; however, there is significant device to device variability in the response of the ferroelectric to a partially switching program pulse, which may require the use of feedback in programming. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | Challenges to Partial Switching of Hf0.8Zr0.2O2 Gated Ferroelectric FET for Multilevel/Analog or Low-voltage Memory Operation | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Kwon, Daewoong | - |
dc.identifier.doi | 10.1109/LED.2019.2931430 | - |
dc.identifier.scopusid | 2-s2.0-85089476081 | - |
dc.identifier.wosid | 000483014600020 | - |
dc.identifier.bibliographicCitation | IEEE ELECTRON DEVICE LETTERS, v.40, no.9, pp.1423 - 1426 | - |
dc.relation.isPartOf | IEEE ELECTRON DEVICE LETTERS | - |
dc.citation.title | IEEE ELECTRON DEVICE LETTERS | - |
dc.citation.volume | 40 | - |
dc.citation.number | 9 | - |
dc.citation.startPage | 1423 | - |
dc.citation.endPage | 1426 | - |
dc.type.rims | ART | - |
dc.type.docType | 정기 학술지(letter(letters to the editor)) | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | Elevated temperature | - |
dc.subject.keywordPlus | Fully depleted silicon-on-insulator | - |
dc.subject.keywordPlus | Gate-last process | - |
dc.subject.keywordPlus | Low voltages | - |
dc.subject.keywordPlus | Memory operations | - |
dc.subject.keywordPlus | Program/erase | - |
dc.subject.keywordPlus | Self-aligned | - |
dc.subject.keywordPlus | Switching program | - |
dc.subject.keywordAuthor | Ferroelectric | - |
dc.subject.keywordAuthor | hafnium zirconium oxide | - |
dc.subject.keywordAuthor | memory | - |
dc.subject.keywordAuthor | gate last | - |
dc.subject.keywordAuthor | silicon-on-insulator | - |
dc.subject.keywordAuthor | neuromorphic computing | - |
dc.subject.keywordAuthor | deep learning | - |
dc.subject.keywordAuthor | artificial intelligence | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/8777131 | - |
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