Double-gate tunnel field-effect transistor with inner doping and spacer regions
DC Field | Value | Language |
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dc.contributor.author | Kim, Hyun Woo | - |
dc.contributor.author | Kwon, Daewoong | - |
dc.date.accessioned | 2023-09-04T19:10:10Z | - |
dc.date.available | 2023-09-04T19:10:10Z | - |
dc.date.created | 2023-07-19 | - |
dc.date.issued | 2020-12 | - |
dc.identifier.issn | 0021-4922 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/190131 | - |
dc.description.abstract | In this study, a tunnel field-effect transistor (FET) with source-side inner doping and a drain-side spacer is proposed to obtain high current drivability and reduced gate-to-drain capacitance, simultaneously. The effects of the inner doping region (region(inner)) are investigated with various lengths (L-ID) and concentrations (N-ID). As the N-ID increases, the more source-to-region(inner) tunneling is added to conventional source-to-channel tunneling and thus the total tunneling current is enhanced. Moreover, with a wider L-ID, the on-current is reduced by the wider source-to-region(inner) tunneling width and the source-to-region(inner) tunneling is generated at a lower gate voltage by the L-ID-induced limitation of energy band bending. Also, the impact of the inner spacer is evaluated with various inner spacer lengths (L-IS). By introducing the inner spacer, the gate-to-drain capacitance can be significantly reduced. Consequently, the proposed tunnel FET has a reduced gate-to-drain capacitance as well as an increased tunneling current, which leads an improvement in switching delay. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IOP PUBLISHING LTD | - |
dc.title | Double-gate tunnel field-effect transistor with inner doping and spacer regions | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Kwon, Daewoong | - |
dc.identifier.doi | 10.35848/1347-4065/abc926 | - |
dc.identifier.scopusid | 2-s2.0-85097923254 | - |
dc.identifier.wosid | 000592685500001 | - |
dc.identifier.bibliographicCitation | JAPANESE JOURNAL OF APPLIED PHYSICS, v.59, no.12, pp.126505-1 - 126505-7 | - |
dc.relation.isPartOf | JAPANESE JOURNAL OF APPLIED PHYSICS | - |
dc.citation.title | JAPANESE JOURNAL OF APPLIED PHYSICS | - |
dc.citation.volume | 59 | - |
dc.citation.number | 12 | - |
dc.citation.startPage | 126505-1 | - |
dc.citation.endPage | 126505-7 | - |
dc.type.rims | ART | - |
dc.type.docType | 정기학술지(Article(Perspective Article포함)) | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Physics | - |
dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
dc.subject.keywordPlus | NEGATIVE CAPACITANCE FET | - |
dc.subject.keywordPlus | DEVICE | - |
dc.subject.keywordPlus | IMPACT | - |
dc.subject.keywordPlus | PERFORMANCE | - |
dc.subject.keywordPlus | VOLTAGE | - |
dc.subject.keywordAuthor | Tunnel FET | - |
dc.subject.keywordAuthor | subthreshold swing | - |
dc.subject.keywordAuthor | band-to-band tunneling | - |
dc.identifier.url | https://iopscience.iop.org/article/10.35848/1347-4065/abc926 | - |
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