Double-gate tunnel field-effect transistor with inner doping and spacer regions

Abstract

In this study, a tunnel field-effect transistor (FET) with source-side inner doping and a drain-side spacer is proposed to obtain high current drivability and reduced gate-to-drain capacitance, simultaneously. The effects of the inner doping region (region(inner)) are investigated with various lengths (L-ID) and concentrations (N-ID). As the N-ID increases, the more source-to-region(inner) tunneling is added to conventional source-to-channel tunneling and thus the total tunneling current is enhanced. Moreover, with a wider L-ID, the on-current is reduced by the wider source-to-region(inner) tunneling width and the source-to-region(inner) tunneling is generated at a lower gate voltage by the L-ID-induced limitation of energy band bending. Also, the impact of the inner spacer is evaluated with various inner spacer lengths (L-IS). By introducing the inner spacer, the gate-to-drain capacitance can be significantly reduced. Consequently, the proposed tunnel FET has a reduced gate-to-drain capacitance as well as an increased tunneling current, which leads an improvement in switching delay.