Demonstration of Tunneling Field-Effect Transistor Ternary Inverter
DC Field | Value | Language |
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dc.contributor.author | Kim, Hyun Woo | - |
dc.contributor.author | Kim, Sihyun | - |
dc.contributor.author | Lee, Kitae | - |
dc.contributor.author | Lee, Junil | - |
dc.contributor.author | Park, Byung-Gook | - |
dc.contributor.author | Kwon, Daewoong | - |
dc.date.accessioned | 2023-09-04T19:10:23Z | - |
dc.date.available | 2023-09-04T19:10:23Z | - |
dc.date.created | 2023-07-19 | - |
dc.date.issued | 2020-10 | - |
dc.identifier.issn | 0018-9383 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/190133 | - |
dc.description.abstract | We demonstrate tunnel FET (TFET)-based ternaryCMOS (T-CMOS) which can operate at supply voltage (V-DD) < 0.6 V. The TFET T-CMOS consists of the vertical n/p TFETs and their drain current (I-D)-gate voltage (V-G) characteristics have sub-60mV/dec steep subthreshold swing (SS) and hump as the gate and source are overlapped. To verify the formation mechanism of the third output voltage state (V-3rd) in the TFET T-CMOS, I-D-V(G)s are analyzed with respect to various drain voltages (V-D). As a result, it is revealed that I-D-V(G)s of the n/p TFETs can have the wider flat ON-current regions at smaller VD by drain-side channel inversion and stable V-3rd can be formed through the voltage dividing between them. Furthermore, it is found that the hump plays a role to make the steeper output voltage transitions by increasing the I-D difference between the n/p TFETs. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | Demonstration of Tunneling Field-Effect Transistor Ternary Inverter | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Kwon, Daewoong | - |
dc.identifier.doi | 10.1109/TED.2020.3017186 | - |
dc.identifier.scopusid | 2-s2.0-85092194613 | - |
dc.identifier.wosid | 000572635400098 | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON ELECTRON DEVICES, v.67, no.10, pp.4541 - 4544 | - |
dc.relation.isPartOf | IEEE TRANSACTIONS ON ELECTRON DEVICES | - |
dc.citation.title | IEEE TRANSACTIONS ON ELECTRON DEVICES | - |
dc.citation.volume | 67 | - |
dc.citation.number | 10 | - |
dc.citation.startPage | 4541 | - |
dc.citation.endPage | 4544 | - |
dc.type.rims | ART | - |
dc.type.docType | 정기학술지(Article(Perspective Article포함)) | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalResearchArea | Physics | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
dc.subject.keywordPlus | PERFORMANCE | - |
dc.subject.keywordPlus | FET | - |
dc.subject.keywordAuthor | Ternary inverter | - |
dc.subject.keywordAuthor | TFET ternary CMOS (T-CMOS) | - |
dc.subject.keywordAuthor | tunnel FETs (TFET) | - |
dc.subject.keywordAuthor | vertical TFET | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/9180302 | - |
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