Demonstration of Tunneling Field-Effect Transistor Ternary Inverter

Abstract

We demonstrate tunnel FET (TFET)-based ternaryCMOS (T-CMOS) which can operate at supply voltage (V-DD) < 0.6 V. The TFET T-CMOS consists of the vertical n/p TFETs and their drain current (I-D)-gate voltage (V-G) characteristics have sub-60mV/dec steep subthreshold swing (SS) and hump as the gate and source are overlapped. To verify the formation mechanism of the third output voltage state (V-3rd) in the TFET T-CMOS, I-D-V(G)s are analyzed with respect to various drain voltages (V-D). As a result, it is revealed that I-D-V(G)s of the n/p TFETs can have the wider flat ON-current regions at smaller VD by drain-side channel inversion and stable V-3rd can be formed through the voltage dividing between them. Furthermore, it is found that the hump plays a role to make the steeper output voltage transitions by increasing the I-D difference between the n/p TFETs.