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A 16-Gb/s/wire 4-Wire Short-Haul Transceiver with Balanced Single-Ended Signaling (BASES) in 28-nm CMOS
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Kim, Hyochang | - |
| dc.contributor.author | Seo, Hyeongmin | - |
| dc.contributor.author | 김현태 | - |
| dc.contributor.author | Yoo, Changsik | - |
| dc.contributor.author | Han, Jaeduk | - |
| dc.date.accessioned | 2023-09-26T07:30:03Z | - |
| dc.date.available | 2023-09-26T07:30:03Z | - |
| dc.date.issued | 2023-08 | - |
| dc.identifier.issn | 1549-7747 | - |
| dc.identifier.issn | 1558-3791 | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/191035 | - |
| dc.description.abstract | This paper presents a 4-wire, 3-level, and 16-Gb/s/wire transceiver array for short-reach interconnects. The proposed transceiver adopts the balanced single-ended signaling (BASES) to reduce the simultaneous switching noise (SSN) and the electro-magnetic interference (EMI). The four transmit encoders and voltage-mode drivers produce three-level, common-mode-balanced, and multi-lane signals. The receive terminations and equalizers utilize the CM-balancing property of the BASES coding to recover the transmitted signals with a high noise rejection capability. The 4-wire transceiver was fabricated in a 28-nm CMOS technology and achieved a 64-Gb/s aggregate data rate with 3.15-pJ/bit energy efficiency. | - |
| dc.format.extent | 5 | - |
| dc.language | 영어 | - |
| dc.language.iso | ENG | - |
| dc.publisher | Institute of Electrical and Electronics Engineers | - |
| dc.title | A 16-Gb/s/wire 4-Wire Short-Haul Transceiver with Balanced Single-Ended Signaling (BASES) in 28-nm CMOS | - |
| dc.type | Article | - |
| dc.publisher.location | 미국 | - |
| dc.identifier.doi | 10.1109/TCSII.2023.3248633 | - |
| dc.identifier.scopusid | 2-s2.0-85149361651 | - |
| dc.identifier.wosid | 001043666500017 | - |
| dc.identifier.bibliographicCitation | IEEE Transactions on Circuits and Systems II: Express Briefs, v.70, no.8, pp 2799 - 2803 | - |
| dc.citation.title | IEEE Transactions on Circuits and Systems II: Express Briefs | - |
| dc.citation.volume | 70 | - |
| dc.citation.number | 8 | - |
| dc.citation.startPage | 2799 | - |
| dc.citation.endPage | 2803 | - |
| dc.type.docType | Article | - |
| dc.description.isOpenAccess | N | - |
| dc.description.journalRegisteredClass | scie | - |
| dc.description.journalRegisteredClass | scopus | - |
| dc.relation.journalResearchArea | Engineering | - |
| dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
| dc.subject.keywordPlus | NOISE | - |
| dc.subject.keywordAuthor | Single-end signaling | - |
| dc.subject.keywordAuthor | balanced coding | - |
| dc.subject.keywordAuthor | 4-bit 4-wire BASES coding | - |
| dc.subject.keywordAuthor | parallel link | - |
| dc.subject.keywordAuthor | memory interface | - |
| dc.subject.keywordAuthor | simultaneous switching noise (SSN) | - |
| dc.subject.keywordAuthor | electro-magnetic interference (EMI) | - |
| dc.subject.keywordAuthor | common-mode distortions | - |
| dc.subject.keywordAuthor | transceiver | - |
| dc.identifier.url | https://ieeexplore.ieee.org/document/10052690 | - |
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