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Negative capacitance, n-channel, Si FinFETs: Bi-directional sub-60 mV/dec, negative DIBL, negative differential resistance and improved short channel effect

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dc.contributor.authorZhou, Hong-
dc.contributor.authorKwon, Daewoong-
dc.contributor.authorSachid, Angada B.-
dc.contributor.authorLiao, Yuhung-
dc.contributor.authorChatterjee, Korok-
dc.contributor.authorTan, Ava J-
dc.contributor.authorYadav, Ajay K.-
dc.contributor.authorHu, Chenming-
dc.contributor.authorSalahuddin, Sayeef-
dc.date.accessioned2023-09-26T10:20:00Z-
dc.date.available2023-09-26T10:20:00Z-
dc.date.created2023-07-07-
dc.date.issued2018-06-
dc.identifier.issn0743-1562-
dc.identifier.urihttps://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/191518-
dc.description.abstractWe report on negative capacitance (NC) FinFETs with ferroelectric Hf0.5Zr0.5O2 (HZO) as gate dielectric on fully depleted silicon on insulator (FDSOI) substrate with various channel length (LCH) of 450 nm to 30 nm and multiple fin widths (WFIN) of 200 nm to 30 nm. We demonstrate all signature characteristics expected from NCFET: nearly hysteresis free operation (∼3 mV), <60 mV/decade subthreshold swing (SS) with an average SS of 54.5 mV/dec for ∼2 orders of ID and to the best of our knowledge, for the first time in Si MOSFETs, negative Drain Induced Barrier Lowering (DIBL) and Negative Differential Resistance (NDR). Remarkably, we observe significant improvement in the short channel effect compared to control FinFETs: both SS and DIBL are substantially lower for the NCFET for the same Lch/WFin ratio. Importantly, these benefits become increasingly larger for shorter channel lengths.-
dc.language영어-
dc.language.isoen-
dc.publisherInstitute of Electrical and Electronics Engineers-
dc.titleNegative capacitance, n-channel, Si FinFETs: Bi-directional sub-60 mV/dec, negative DIBL, negative differential resistance and improved short channel effect-
dc.typeArticle-
dc.contributor.affiliatedAuthorKwon, Daewoong-
dc.identifier.doi10.1109/VLSIT.2018.8510691-
dc.identifier.scopusid2-s2.0-85056899389-
dc.identifier.bibliographicCitationDIGEST OF TECHNICAL PAPERS - SYMPOSIUM ON VLSI TECHNOLOGY, v.2018-June, pp.53 - 54-
dc.relation.isPartOfDIGEST OF TECHNICAL PAPERS - SYMPOSIUM ON VLSI TECHNOLOGY-
dc.citation.titleDIGEST OF TECHNICAL PAPERS - SYMPOSIUM ON VLSI TECHNOLOGY-
dc.citation.volume2018-June-
dc.citation.startPage53-
dc.citation.endPage54-
dc.type.rimsART-
dc.type.docTypeProceeding-
dc.description.journalClass1-
dc.description.isOpenAccessN-
dc.description.journalRegisteredClassscopus-
dc.subject.keywordPlusCapacitance-
dc.subject.keywordPlusFinFET-
dc.subject.keywordPlusGate dielectrics-
dc.subject.keywordPlusNegative resistance-
dc.subject.keywordPlusSilicon on insulator technology-
dc.subject.keywordPlusThreshold voltage-
dc.subject.keywordPlusVLSI circuits-
dc.subject.keywordPlusZirconium compounds-
dc.identifier.urlhttps://ieeexplore.ieee.org/document/8510691-
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