Construction of Cyclic Redundancy Check Codes for SDDC Decoding in DRAM Systems

Abstract

Single device data correction (SDDC) is a main reliability, availability, and serviceability feature of DRAM systems in servers due to the significant hard-failure rate associated with DRAM devices. To correct errors in one DRAM device, error pattern is determined by even parity bits and error location is determined by the error pattern and cyclic redundancy check (CRC) bits in SDDC decoding. In this brief, a SDDC decoding scheme is proposed, which improves the error-correction performance by uniquely determining the error location. For that purpose, requirements for binary CRC generator polynomials to uniquely determine the error location are derived. Based on these requirements, a systematic method for constructing CRC generator polynomials is proposed, which guarantees 100% error-correction rate. Finally, it is confirmed that the proposed SDDC decoding scheme has lower decoding complexity compared with various ECC schemes and also shows 100% SDDC decoding success through simulation.