Analysis of the Role of Interfacial Layer in Ferroelectric FET Failure as a Memory Cell

Abstract

By observing temporary and permanent changes in threshold voltage (<italic>V</italic>T) due to the application of unipolar/bipolar stress, it was confirmed that the trap-carrier interaction speed is the cause of failure of the ferroelectric transistor as a memory. As the polarization switching occurs, carriers are trapped in the ferroelectric/interfacial layer (FE/IL), and the hole trap is limited compared to the electron trap due to the slow interaction. IL degrades under bipolar stress due to the high electric field during polarization switching, leading to the acceleration of hole trapping, which has a strong impact on the memory window.

By observing temporary and permanent changes in threshold voltage (VT) due to the application of unipolar/bipolar stress, it was confirmed that the trap-carrier interaction speed is the cause of failure of the ferroelectric transistor as a memory. As the polarization switching occurs, carriers are trapped in the ferroelectric/interfacial layer (FE/IL), and the hole trap is limited compared to the electron trap due to the slow interaction. IL degrades under bipolar stress due to the high electric field during polarization switching, leading to the acceleration of hole trapping, which has a strong impact on the memory window.