Analysis of Nanosheet Field-Effect Transistor With Local Bottom Isolation

Abstract

We propose a three-channel-based nanosheetfield-effect transistor (BO NSFET3-channel) adopting abottom isolation (BO) under inner gate regions to allevi-ate subleakage current as well as parasitic capacitance, simultaneously. To thoroughly evaluate the superiority ofthe proposed device, the conventional four-channel-basedNSFETs were used with punchthrough stop (PTS) dop-ing (NSFET4-channel) and BO scheme (BO NSFET4-channel)as references, and the electrical characteristics for each device were investigated using the 3-D technologycomputer-aided design (TCAD) simulations. For the pro-posed BO NSFET3-channel, although the PTS doping was not applied, it was observed that off-current and subthresh-old swing (SS) characteristics are almost the same with the conventional NSFET4-channel with PTS doping because BO scheme can physically suppress direct source-to-drain leakage. It can also have less gate-induced drain leakage (GIDL) between the inner gate and substrate by BO schemeand small drain-to-substrate junction leakages by PTS dop-ing skip. Furthermore, it was revealed that parasitic gateoxide capacitances are decreased about 9.03% comparedto the references by adding the BO scheme under theinner gates, which hinders the bottom channel formation. As a result, it was confirmed that the intrinsic delay ofthe proposed device is improved 7.1% at I-D,I-OFF=2 nA/mu m compared to the conventional one. This proposed BO scheme would be beneficial for both n- and p-type NSFET devices and can provide valuable insights for the design ofthe next-generation logic devices.