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In-depth Analysis of the Hafnia Ferroelectrics as a Key Enabler for Low Voltage & QLC 3D VNAND beyond 1K Layers: Experimental Demonstration and Modeling

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dc.contributor.authorKim, Giuk-
dc.contributor.authorChoi, Hyojun-
dc.contributor.authorShin, Hunbeom-
dc.contributor.authorLee, Sangho-
dc.contributor.authorLee, Sangmok-
dc.contributor.authorNam, Yunseok-
dc.contributor.authorJung, Minhyun-
dc.contributor.authorMyeong, Ilho-
dc.contributor.authorKim, Kijoon-
dc.contributor.authorWoo, Jongho-
dc.contributor.authorLim, Suhwan-
dc.contributor.authorKim, Kwangsoo-
dc.contributor.authorKim, Wanki-
dc.contributor.authorHa, Daewon-
dc.contributor.authorAhn, Jinho-
dc.contributor.authorJeon, Sanghun-
dc.date.accessioned2024-11-28T08:36:01Z-
dc.date.available2024-11-28T08:36:01Z-
dc.date.issued2024-06-
dc.identifier.issn0743-1562-
dc.identifier.urihttps://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/195335-
dc.description.abstractIn this work, we experimentally demonstrate a remarkable performance improvement, boosted by the interaction of charge trapping & ferroelectric (FE) switching effects in metal-band engineered gate interlayer (BE-G.IL)- FE-channel interlayer (Ch.IL)-Si (MIFIS) FeFET. The MIFIS with BE-G.IL (BE-MIFIS) facilitates the maximized 'positive feedback' (Posi. FB.) of dual effects, leading to low operation voltage (VPGM/VERS: +17/-15 V), a wide memory window (MW: 10.5 V) and negligible disturb at a biased voltage of 9 V. Furthermore, our proposed model verifies that the performance enhancement of the BE-MIFIS FeFET is attributed to the intensified posi. FB. This work proves that the hafnia FE can play as a key enabler in extending the technology development of 3D VNAND, which is currently approaching a state of stagnation.-
dc.format.extent2-
dc.language영어-
dc.language.isoENG-
dc.titleIn-depth Analysis of the Hafnia Ferroelectrics as a Key Enabler for Low Voltage & QLC 3D VNAND beyond 1K Layers: Experimental Demonstration and Modeling-
dc.typeArticle-
dc.identifier.doi10.1109/VLSITechnologyandCir46783.2024.10631559-
dc.identifier.scopusid2-s2.0-85203587565-
dc.identifier.bibliographicCitationDigest of Technical Papers - Symposium on VLSI Technology, pp 1 - 2-
dc.citation.titleDigest of Technical Papers - Symposium on VLSI Technology-
dc.citation.startPage1-
dc.citation.endPage2-
dc.type.docTypeConference paper-
dc.description.isOpenAccessN-
dc.description.journalRegisteredClassscopus-
dc.subject.keywordPlusFerroelectric ceramics-
dc.subject.keywordPlusJunction gate field effect transistors-
dc.subject.keywordPlusLow power electronics-
dc.subject.keywordPlusMIM devices-
dc.subject.keywordPlusSystem-on-chip-
dc.subject.keywordPlusThree dimensional integrated circuits-
dc.identifier.urlhttps://ieeexplore.ieee.org/document/10631559-
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