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In-depth Analysis of the Hafnia Ferroelectrics as a Key Enabler for Low Voltage & QLC 3D VNAND beyond 1K Layers: Experimental Demonstration and Modeling
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Kim, Giuk | - |
| dc.contributor.author | Choi, Hyojun | - |
| dc.contributor.author | Shin, Hunbeom | - |
| dc.contributor.author | Lee, Sangho | - |
| dc.contributor.author | Lee, Sangmok | - |
| dc.contributor.author | Nam, Yunseok | - |
| dc.contributor.author | Jung, Minhyun | - |
| dc.contributor.author | Myeong, Ilho | - |
| dc.contributor.author | Kim, Kijoon | - |
| dc.contributor.author | Woo, Jongho | - |
| dc.contributor.author | Lim, Suhwan | - |
| dc.contributor.author | Kim, Kwangsoo | - |
| dc.contributor.author | Kim, Wanki | - |
| dc.contributor.author | Ha, Daewon | - |
| dc.contributor.author | Ahn, Jinho | - |
| dc.contributor.author | Jeon, Sanghun | - |
| dc.date.accessioned | 2024-11-28T08:36:01Z | - |
| dc.date.available | 2024-11-28T08:36:01Z | - |
| dc.date.issued | 2024-06 | - |
| dc.identifier.issn | 0743-1562 | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/195335 | - |
| dc.description.abstract | In this work, we experimentally demonstrate a remarkable performance improvement, boosted by the interaction of charge trapping & ferroelectric (FE) switching effects in metal-band engineered gate interlayer (BE-G.IL)- FE-channel interlayer (Ch.IL)-Si (MIFIS) FeFET. The MIFIS with BE-G.IL (BE-MIFIS) facilitates the maximized 'positive feedback' (Posi. FB.) of dual effects, leading to low operation voltage (VPGM/VERS: +17/-15 V), a wide memory window (MW: 10.5 V) and negligible disturb at a biased voltage of 9 V. Furthermore, our proposed model verifies that the performance enhancement of the BE-MIFIS FeFET is attributed to the intensified posi. FB. This work proves that the hafnia FE can play as a key enabler in extending the technology development of 3D VNAND, which is currently approaching a state of stagnation. | - |
| dc.format.extent | 2 | - |
| dc.language | 영어 | - |
| dc.language.iso | ENG | - |
| dc.title | In-depth Analysis of the Hafnia Ferroelectrics as a Key Enabler for Low Voltage & QLC 3D VNAND beyond 1K Layers: Experimental Demonstration and Modeling | - |
| dc.type | Article | - |
| dc.identifier.doi | 10.1109/VLSITechnologyandCir46783.2024.10631559 | - |
| dc.identifier.scopusid | 2-s2.0-85203587565 | - |
| dc.identifier.bibliographicCitation | Digest of Technical Papers - Symposium on VLSI Technology, pp 1 - 2 | - |
| dc.citation.title | Digest of Technical Papers - Symposium on VLSI Technology | - |
| dc.citation.startPage | 1 | - |
| dc.citation.endPage | 2 | - |
| dc.type.docType | Conference paper | - |
| dc.description.isOpenAccess | N | - |
| dc.description.journalRegisteredClass | scopus | - |
| dc.subject.keywordPlus | Ferroelectric ceramics | - |
| dc.subject.keywordPlus | Junction gate field effect transistors | - |
| dc.subject.keywordPlus | Low power electronics | - |
| dc.subject.keywordPlus | MIM devices | - |
| dc.subject.keywordPlus | System-on-chip | - |
| dc.subject.keywordPlus | Three dimensional integrated circuits | - |
| dc.identifier.url | https://ieeexplore.ieee.org/document/10631559 | - |
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