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Heterogeneous monolithic 3D integration for hybrid vertical CMOS inverter using n-type IGTO TFT on p-type Si FET

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dc.contributor.authorLee, Chanseul-
dc.contributor.authorKim, Sunbum-
dc.contributor.authorKim, Gyulee-
dc.contributor.authorChoi, Changhwan-
dc.date.accessioned2024-11-28T08:36:02Z-
dc.date.available2024-11-28T08:36:02Z-
dc.date.issued2025-01-
dc.identifier.issn1369-8001-
dc.identifier.issn1873-4081-
dc.identifier.urihttps://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/195336-
dc.description.abstractIn this work, a complementary metal oxide semiconductor (CMOS) vertical inverter using heterogeneous monolithic 3D (M3D) integration with p-type Si field-effect transistor (FET) and n-type indium-gallium-tin-oxide (IGTO) thin film transistor (TFT) was implemented and characterized. This CMOS inverter was attained by vertical stacking n-type IGTO TFT on p-type Si FET. Oxide semiconductor materials such as indium-gallium-zinc-oxide (IGZO), indium-tungsten-oxide (IWO), indium oxide (In2O3) and IGTO are being considered as potential options for channel materials in M3D integration technology due to high electrical characteristics and low temperature process. Among them, IGTO was employed as a channel material to achieve high mobility. We fabricated a n-type IGTO TFT using HfO2 and tungsten as a gate dielectric and electrode, respectively. The post-annealing process was conducted at 200–500 °C with 50 °C intervals. The IGTO TFT exhibits a high field-effect mobility (32.9 cm2/Vs), low sub-threshold swing (0.070 V/dec) and stable reliability behaviour (ΔVth < 0.4 V) against various external gate bias temperature stress tests in a low temperature (<500 °C). The stable heterogeneous vertical inverter performance such as voltage-transfer curve (VM = 1.66 V), voltage gain (30.1 V at VDD = 3 V), and noise margin (NMH = 1.22 V, NML = 1.34 V) were well behaved. This M3D integration-based hybrid CMOS inverter can be an alternative knob toward various device applications.-
dc.format.extent9-
dc.language영어-
dc.language.isoENG-
dc.publisherPergamon Press-
dc.titleHeterogeneous monolithic 3D integration for hybrid vertical CMOS inverter using n-type IGTO TFT on p-type Si FET-
dc.typeArticle-
dc.publisher.location영국-
dc.identifier.doi10.1016/j.mssp.2024.108871-
dc.identifier.scopusid2-s2.0-85203428561-
dc.identifier.wosid001314257100001-
dc.identifier.bibliographicCitationMaterials Science in Semiconductor Processing, v.185, pp 1 - 9-
dc.citation.titleMaterials Science in Semiconductor Processing-
dc.citation.volume185-
dc.citation.startPage1-
dc.citation.endPage9-
dc.type.docTypeArticle-
dc.description.isOpenAccessN-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalResearchAreaMaterials Science-
dc.relation.journalResearchAreaPhysics-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.relation.journalWebOfScienceCategoryMaterials Science, Multidisciplinary-
dc.relation.journalWebOfScienceCategoryPhysics, Applied-
dc.relation.journalWebOfScienceCategoryPhysics, Condensed Matter-
dc.subject.keywordPlusTHIN-FILM TRANSISTORS-
dc.subject.keywordPlusPHOTO-BIAS INSTABILITY-
dc.subject.keywordPlusHIGH-PERFORMANCE-
dc.subject.keywordPlusHIGH-MOBILITY-
dc.subject.keywordPlus3-D-
dc.subject.keywordPlusCIRCUITS-
dc.subject.keywordPlusCONTACT-
dc.subject.keywordPlusCHANNEL-
dc.subject.keywordPlusVOLTAGE-
dc.subject.keywordAuthorHeterogeneous integration-
dc.subject.keywordAuthorIGTO TFT-
dc.subject.keywordAuthorInverter-
dc.subject.keywordAuthorMonolithic 3D (M3D)-
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COLLEGE OF ENGINEERING (SCHOOL OF MATERIALS SCIENCE AND ENGINEERING)
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