Lightweight Polynomial Multiplication Accelerator for NTRU Using Shared SRAM

Abstract

Established in 1996, NTRU was standardized according to IEEE P1363.1 and ANSI X9.98 and has been in use for a long time. This brief presents a lightweight accelerator which supports NTRU’s main operation, polynomial multiplication. The proposed accelerator is embedded within the slave wrapper of the static random-access memory (SRAM) rather than using a dedicated memory and can directly access the SRAM, eliminating data transfer and data redundancy between the SRAM and the accelerator. This helps in reducing the latency and the required resources. In this study, we focus on the NTRU version submitted to the National Institute of Standards and Technology (NIST) post-quantum cryptography standardization process. This version contains four parameter sets, which are all supported by the proposed accelerator. The accelerator can be synthesized at a clock frequency of 270 MHz, requires only 17.3 k gate counts, and can perform encryption and decryption within 0.1 and 1.5 ms, respectively. The proposed accelerator is expected to be implemented in resource-constrained applications such as Internet of Things.