LAYGO2: A Custom Layout Generation Engine Based on Dynamic Templates and Grids for Advanced CMOS Technologies

Abstract

This article presents an automatic layout generation framework in advanced CMOS technologies. The framework extends the template-and-grid-based layout generation methodology to produce optimal layouts more efficiently. Layout templates and grids are dynamically created and adjusted during the generation phase to provide more reusability and flexibility. Virtual instances are used to encapsulate the dynamically generated layout structures. Internal node probes embedded in the dynamic templates capture parasitic effects precisely. The framework also implements various post-processing functions to handle process-specific tasks while maintaining the overall process portability of procedural layout generators. The post-processing functions include cut/dummy pattern generation and multiple-patterning adjustment. The generator description coverage is enhanced with circular grid indexing/slicing and conditional conversion operators. The layout generation framework is applied to generate various DRC/LVS clean layouts automatically in advanced CMOS technologies, achieving 0.66-249.35 transistors-per-line (the ratio of the generated transistor count to the source lines of code) generation efficiencies.