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An Analysis of Current-mode Drivers in 40-nm CMOS Technology
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Lim, Bona | - |
| dc.contributor.author | Jo, Hanhee | - |
| dc.contributor.author | Han, Jaeduk | - |
| dc.date.accessioned | 2024-11-28T13:31:36Z | - |
| dc.date.available | 2024-11-28T13:31:36Z | - |
| dc.date.issued | 2023-10 | - |
| dc.identifier.issn | 2163-9612 | - |
| dc.identifier.issn | 2472-9655 | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/196664 | - |
| dc.description.abstract | This paper compares two prominent high-speed link transmitter driver topologies, cascode current-mode logic (CML) and tailless CML, exploring their design tradeoffs. Analysis and simulation results reveal that the cascode CML exhibits higher output resistance due to the presence of a tail current source, while the tailless CML demonstrates faster operation with reduced output capacitance. Additionally, this study highlights the tradeoff between driver output swing and power consumption. | - |
| dc.format.extent | 2 | - |
| dc.language | 영어 | - |
| dc.language.iso | ENG | - |
| dc.publisher | IEEE | - |
| dc.title | An Analysis of Current-mode Drivers in 40-nm CMOS Technology | - |
| dc.type | Article | - |
| dc.publisher.location | 미국 | - |
| dc.identifier.doi | 10.1109/ISOCC59558.2023.10396410 | - |
| dc.identifier.scopusid | 2-s2.0-85184821959 | - |
| dc.identifier.wosid | 001169439300167 | - |
| dc.identifier.bibliographicCitation | Proceedings - International SoC Design Conference 2023, ISOCC 2023, pp 355 - 356 | - |
| dc.citation.title | Proceedings - International SoC Design Conference 2023, ISOCC 2023 | - |
| dc.citation.startPage | 355 | - |
| dc.citation.endPage | 356 | - |
| dc.type.docType | Proceedings Paper | - |
| dc.description.isOpenAccess | N | - |
| dc.description.journalRegisteredClass | scopus | - |
| dc.subject.keywordPlus | Analog circuits | - |
| dc.subject.keywordPlus | Cascode amplifiers | - |
| dc.subject.keywordPlus | CMOS integrated circuits | - |
| dc.subject.keywordPlus | Computer circuits | - |
| dc.subject.keywordPlus | Electric resistance | - |
| dc.subject.keywordPlus | Integrated circuit design | - |
| dc.subject.keywordAuthor | cascode current-mode logic (CML) | - |
| dc.subject.keywordAuthor | design tradeoffs | - |
| dc.subject.keywordAuthor | high-speed link transmitters | - |
| dc.subject.keywordAuthor | tailless CML | - |
| dc.identifier.url | https://ieeexplore.ieee.org/document/10396410 | - |
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