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Novel strategies for low-voltage NAND flash memory with negative capacitance effect

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dc.contributor.authorKim, Giuk-
dc.contributor.authorKim, Taeho-
dc.contributor.authorLee, Sangho-
dc.contributor.authorHwang, Junghyeon-
dc.contributor.authorJung, Minhyun-
dc.contributor.authorAhn, Jinho-
dc.contributor.authorJeon, Sanghun-
dc.date.accessioned2024-11-28T15:31:26Z-
dc.date.available2024-11-28T15:31:26Z-
dc.date.issued2024-05-
dc.identifier.issn0021-4922-
dc.identifier.issn1347-4065-
dc.identifier.urihttps://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/197279-
dc.description.abstractHere, we present a novel approach to employing a negative capacitance (NC) phenomenon in the blocking oxide of charge trap flash (CTF) memory. To achieve this, we developed an inversible mono-domain like ferroelectric (IMFE) film through high-pressure post-deposition annealing in a forming gas at 200 atm (FG-HPPDA). The FG-HPPDA process enables to form a uniform alignment of domains and facilitates invertible domain switching behavior in ferroelectrics, generating an internal field by the flexo-electric effect as well as interface-pinned polarization by chemical reaction. Subsequently, to stabilize the NC effect, we fabricated the IMFE/Al2O3 heterostructure, which exhibits an outstanding capacitance-boosting feature. Finally, we successfully demonstrate unprecedented CTF memory with the NC effect in a blocking oxide. Our unique CTF device shows the improved performance (maximum incremental-step-pulse-programming (ISPP) slope ∼1.05) and a large MW (>8 V), attributed to the capacitance boosting by NC phenomenon.-
dc.format.extent5-
dc.language영어-
dc.language.isoENG-
dc.publisherIOP Publishing Ltd-
dc.titleNovel strategies for low-voltage NAND flash memory with negative capacitance effect-
dc.typeArticle-
dc.publisher.location영국-
dc.identifier.doi10.35848/1347-4065/ad3f23-
dc.identifier.scopusid2-s2.0-85192682798-
dc.identifier.wosid001215219200001-
dc.identifier.bibliographicCitationJapanese Journal of Applied Physics, v.63, no.5, pp 1 - 5-
dc.citation.titleJapanese Journal of Applied Physics-
dc.citation.volume63-
dc.citation.number5-
dc.citation.startPage1-
dc.citation.endPage5-
dc.type.docTypeArticle-
dc.description.isOpenAccessN-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaPhysics-
dc.relation.journalWebOfScienceCategoryPhysics, Applied-
dc.subject.keywordPlusCharge trapping-
dc.subject.keywordPlusFerroelectric materials-
dc.subject.keywordPlusFerroelectricity-
dc.subject.keywordPlusFlash memory-
dc.subject.keywordPlusMemory architecture-
dc.subject.keywordPlusNAND circuits-
dc.subject.keywordPlusNonvolatile storage-
dc.subject.keywordAuthor3D NAND-
dc.subject.keywordAuthorcharge trap flash-
dc.subject.keywordAuthorlarge memory window-
dc.subject.keywordAuthornegative capacitance-
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