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Novel strategies for low-voltage NAND flash memory with negative capacitance effect
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Kim, Giuk | - |
| dc.contributor.author | Kim, Taeho | - |
| dc.contributor.author | Lee, Sangho | - |
| dc.contributor.author | Hwang, Junghyeon | - |
| dc.contributor.author | Jung, Minhyun | - |
| dc.contributor.author | Ahn, Jinho | - |
| dc.contributor.author | Jeon, Sanghun | - |
| dc.date.accessioned | 2024-11-28T15:31:26Z | - |
| dc.date.available | 2024-11-28T15:31:26Z | - |
| dc.date.issued | 2024-05 | - |
| dc.identifier.issn | 0021-4922 | - |
| dc.identifier.issn | 1347-4065 | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/197279 | - |
| dc.description.abstract | Here, we present a novel approach to employing a negative capacitance (NC) phenomenon in the blocking oxide of charge trap flash (CTF) memory. To achieve this, we developed an inversible mono-domain like ferroelectric (IMFE) film through high-pressure post-deposition annealing in a forming gas at 200 atm (FG-HPPDA). The FG-HPPDA process enables to form a uniform alignment of domains and facilitates invertible domain switching behavior in ferroelectrics, generating an internal field by the flexo-electric effect as well as interface-pinned polarization by chemical reaction. Subsequently, to stabilize the NC effect, we fabricated the IMFE/Al2O3 heterostructure, which exhibits an outstanding capacitance-boosting feature. Finally, we successfully demonstrate unprecedented CTF memory with the NC effect in a blocking oxide. Our unique CTF device shows the improved performance (maximum incremental-step-pulse-programming (ISPP) slope ∼1.05) and a large MW (>8 V), attributed to the capacitance boosting by NC phenomenon. | - |
| dc.format.extent | 5 | - |
| dc.language | 영어 | - |
| dc.language.iso | ENG | - |
| dc.publisher | IOP Publishing Ltd | - |
| dc.title | Novel strategies for low-voltage NAND flash memory with negative capacitance effect | - |
| dc.type | Article | - |
| dc.publisher.location | 영국 | - |
| dc.identifier.doi | 10.35848/1347-4065/ad3f23 | - |
| dc.identifier.scopusid | 2-s2.0-85192682798 | - |
| dc.identifier.wosid | 001215219200001 | - |
| dc.identifier.bibliographicCitation | Japanese Journal of Applied Physics, v.63, no.5, pp 1 - 5 | - |
| dc.citation.title | Japanese Journal of Applied Physics | - |
| dc.citation.volume | 63 | - |
| dc.citation.number | 5 | - |
| dc.citation.startPage | 1 | - |
| dc.citation.endPage | 5 | - |
| dc.type.docType | Article | - |
| dc.description.isOpenAccess | N | - |
| dc.description.journalRegisteredClass | scie | - |
| dc.description.journalRegisteredClass | scopus | - |
| dc.relation.journalResearchArea | Physics | - |
| dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
| dc.subject.keywordPlus | Charge trapping | - |
| dc.subject.keywordPlus | Ferroelectric materials | - |
| dc.subject.keywordPlus | Ferroelectricity | - |
| dc.subject.keywordPlus | Flash memory | - |
| dc.subject.keywordPlus | Memory architecture | - |
| dc.subject.keywordPlus | NAND circuits | - |
| dc.subject.keywordPlus | Nonvolatile storage | - |
| dc.subject.keywordAuthor | 3D NAND | - |
| dc.subject.keywordAuthor | charge trap flash | - |
| dc.subject.keywordAuthor | large memory window | - |
| dc.subject.keywordAuthor | negative capacitance | - |
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