The Effect of Ferroelectric/Dielectric Capacitance Ratio on Short-Term Retention Characteristics of MFMIS FeFETopen access
- Authors
- Hwang, Junghyeon; Kim, Giuk; Joh, Hongrae; Ahn, Jinho; Jeon, Sanghun
- Issue Date
- Oct-2024
- Publisher
- Institute of Electrical and Electronics Engineers Inc.
- Keywords
- Iron; FeFETs; Logic gates; Voltage measurement; Delays; Capacitance; Silicon; Switches; Capacitors; MOS capacitors; Hafnia ferroelectric; ferroelectric FET (FeFET); depolarization field; retention
- Citation
- IEEE Journal of the Electron Devices Society, v.12, pp 988 - 992
- Pages
- 5
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE Journal of the Electron Devices Society
- Volume
- 12
- Start Page
- 988
- End Page
- 992
- URI
- https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/198105
- DOI
- 10.1109/JEDS.2024.3485869
- ISSN
- 2168-6734
2168-6734
- Abstract
- Metal-ferroelectric-metal-insulator-semiconductor (MFMIS) FeFETs have significant potentialfor use in non-volatile memory applications. This is primarily due to their compatibility with CMOStechnology and reliable switching characteristics. Previous studies have primarily concentrated on theendurance and memory window properties, while this study focuses on the short-term (<1 mu s) retentionregion of MFMIS FeFETs. Specifically, we examine the impact of the capacitance ratio of the ferroelectriccapacitor (C-FE) and the MOS capacitor (C-DE) on short-term retention. Additionally, we conductedsimulations to validate the experimental observations and investigate the interaction of the depolarizationfield with the charge trapping and polarization of the MFMIS structure. This study emphasizes the crucialrole of controlling the C-DE:C(FE)ratio in enhancing the short-term retention of MFMIS FeFETs. Its findingsenhance our understanding of short-term retention mechanisms and provide a pathway for improvingperformance and functionality in non-volatile memory technology design.
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