Exploring parallelization techniques based on OpenMP in H.264/AVC encoder for embedded multi-core processor
- Authors
- Jo, Seongmin; Jo, Song Hyun; Song, Yong Ho
- Issue Date
- Oct-2012
- Publisher
- Elsevier BV
- Keywords
- Parallel programming; Multimedia codec; Multi-core processor; Embedded system; Design exploration
- Citation
- Journal of Systems Architecture, v.58, no.9, pp 339 - 353
- Pages
- 15
- Indexed
- SCIE
SCOPUS
- Journal Title
- Journal of Systems Architecture
- Volume
- 58
- Number
- 9
- Start Page
- 339
- End Page
- 353
- URI
- https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/202625
- DOI
- 10.1016/j.sysarc.2012.06.005
- ISSN
- 1383-7621
1873-6165
- Abstract
- Recent advances in semiconductor technologies make it possible to integrate many processor cores in a small device package. The parallel execution capability of such multi-core processors can be exploited to enhance the performance of many traditional sequential applications. There have been numerous research activities to develop parallelization techniques using the OpenMp programming model, in order to speed up sequential applications such as the H.264/AVC codec, but mostly in the PC environment. Therefore, it is difficult to understand which parallelization technique fits well with the H.264/AVC encoder on an embedded multi-core architecture. In this paper, we present parallelization techniques applicable to the H.264/AVC encoder on ARM MPCore using the OpenMP programming model. Further, we propose an analytical model for the performance estimation of the H.264/AVC encoder, and we then verify the model accuracy by performing simulations using hardware/software co-verification tool. Our experimental results show that the parallelization techniques proposed in this paper for the embedded multi-core platform improve the encoder performance by up to 2.36 times, and that the parallelization technique exploiting data-level parallelism outperforms the one using task-level parallelism by 41%. It is also observed that balancing loads among processor cores is a critical parameter in achieving better scalability in the encoder.
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