ASiPEC: An application specific instruction-set processor for high performance entropy coding

Abstract

Entropy coding becomes a performance bottle neck in video codecs because it requires a large amount of bitwise computation. Many video systems accelerate the coding process by implementing it as a hardwired accelerator or by executing it on an extra general-purpose processor to meet performance requirement. However, the variety of video formats causes a high degree of complication to a hardwired accelerator, which increases implementation cost and complexity. When an extra processor is used for the coding process, the property of using variable-length operands in the coding process significantly causes computation inefficiency. This paper presents a novel processor architecture which provides an instruction set suitable for efficient execution of entropy coding process as well as supports for multiple video formats.