Skewed vertical interleaving scheme to improve data reliability in die-stacked DRAM

Abstract

3D die-stacking is a promising technique to address the well-known memory wall problem. As semiconductor processing technology scales down, data reliability become one of the most significant challenges to overcome to build robust memory system. Traditionally, the data reliability in memory has been achieved by employing effective data protection mechanisms such as a physical interleaving. When DRAMs are stacked, same fault tolerant mechanism can be applied to the memory system. However, unlike in 2D memory organization where multi-bit failures occur on the same horizontal plane, in 3D die-stacked DRAM they can occur vertically through multiple dies and the simple application of the physical inter leaving technique is no longer effective. This paper presents a die-stacked DRAM organization that uses the vertical inter leaving scheme to protect against vertical multi-bit failures.