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1-D PE 어레이로 컨볼루션 연산을 수행하는 저전력 DCNN 가속기
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | 이정혁 | - |
| dc.contributor.author | 한상욱 | - |
| dc.contributor.author | 최승원 | - |
| dc.date.accessioned | 2024-12-20T07:47:26Z | - |
| dc.date.available | 2024-12-20T07:47:26Z | - |
| dc.date.issued | 2022-06 | - |
| dc.identifier.issn | 1738-6667 | - |
| dc.identifier.issn | 2713-9018 | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/203620 | - |
| dc.description.abstract | In this paper, we propose a novel method of performing convolutional operations on a 2-D Processing Element(PE) array. The conventional method [1] of mapping the convolutional operation using the 2-D PE array lacks flexibility and provides low utilization of PEs. However, by mapping a convolutional operation from a 2-D PE array to a 1-D PE array, the proposed method can increase the number and utilization of active PEs. Consequently, the throughput of the proposed Deep Convolutional Neural Network(DCNN) accelerator can be increased significantly. Furthermore, the power consumption for the transmission of weights between PEs can be saved. Based on the simulation results, the performance of the proposed method provides approximately 4.55%, 13.7%, and 2.27% throughput gains for each of the convolutional layers of AlexNet, VGG16, and ResNet50 using the DCNN accelerator with a (weights size) x (output data size) 2-D PE array compared to the conventional method. Additionally the proposed method provides approximately 63.21%, 52.46%, and 39.23% power savings. | - |
| dc.format.extent | 10 | - |
| dc.language | 한국어 | - |
| dc.language.iso | KOR | - |
| dc.publisher | (사)디지털산업정보학회 | - |
| dc.title | 1-D PE 어레이로 컨볼루션 연산을 수행하는 저전력 DCNN 가속기 | - |
| dc.title.alternative | Power-Efficient DCNN Accelerator Mapping Convolutional Operation with 1-D PE Array | - |
| dc.type | Article | - |
| dc.publisher.location | 대한민국 | - |
| dc.identifier.doi | 10.17662/ksdim.2022.18.2.017 | - |
| dc.identifier.bibliographicCitation | (사)디지털산업정보학회 논문지, v.18, no.2, pp 17 - 26 | - |
| dc.citation.title | (사)디지털산업정보학회 논문지 | - |
| dc.citation.volume | 18 | - |
| dc.citation.number | 2 | - |
| dc.citation.startPage | 17 | - |
| dc.citation.endPage | 26 | - |
| dc.identifier.kciid | ART002854751 | - |
| dc.description.isOpenAccess | N | - |
| dc.description.journalRegisteredClass | kci | - |
| dc.subject.keywordAuthor | FPGA | - |
| dc.subject.keywordAuthor | Deep Convolutional Neural Network | - |
| dc.subject.keywordAuthor | Accelerator | - |
| dc.subject.keywordAuthor | Processing Element | - |
| dc.subject.keywordAuthor | Data Reuse | - |
| dc.identifier.url | http://koreascience.or.kr/article/JAKO202219441468361.page | - |
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