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1-D PE 어레이로 컨볼루션 연산을 수행하는 저전력 DCNN 가속기Power-Efficient DCNN Accelerator Mapping Convolutional Operation with 1-D PE Array

Other Titles
Power-Efficient DCNN Accelerator Mapping Convolutional Operation with 1-D PE Array
Authors
이정혁한상욱최승원
Issue Date
Jun-2022
Publisher
(사)디지털산업정보학회
Keywords
FPGA; Deep Convolutional Neural Network; Accelerator; Processing Element; Data Reuse
Citation
(사)디지털산업정보학회 논문지, v.18, no.2, pp 17 - 26
Pages
10
Indexed
KCI
Journal Title
(사)디지털산업정보학회 논문지
Volume
18
Number
2
Start Page
17
End Page
26
URI
https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/203620
DOI
10.17662/ksdim.2022.18.2.017
ISSN
1738-6667
2713-9018
Abstract
In this paper, we propose a novel method of performing convolutional operations on a 2-D Processing Element(PE) array. The conventional method [1] of mapping the convolutional operation using the 2-D PE array lacks flexibility and provides low utilization of PEs. However, by mapping a convolutional operation from a 2-D PE array to a 1-D PE array, the proposed method can increase the number and utilization of active PEs. Consequently, the throughput of the proposed Deep Convolutional Neural Network(DCNN) accelerator can be increased significantly. Furthermore, the power consumption for the transmission of weights between PEs can be saved. Based on the simulation results, the performance of the proposed method provides approximately 4.55%, 13.7%, and 2.27% throughput gains for each of the convolutional layers of AlexNet, VGG16, and ResNet50 using the DCNN accelerator with a (weights size) x (output data size) 2-D PE array compared to the conventional method. Additionally the proposed method provides approximately 63.21%, 52.46%, and 39.23% power savings.
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서울 공과대학 > 서울 융합전자공학부 > 1. Journal Articles
서울 공과대학 > 서울 건설환경공학과 > 1. Journal Articles

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