Reduction of trap density in high-k dielectrics through optimized ALD process and high-pressure deuterium annealing

Abstract

The scaling down of transistors has increased the need for high-k dielectric materials to suppress the quantum mechanical tunneling through thin insulator layers. However, high-k materials are prone to defect formation, which deteriorates their electrical properties. This study proposes two methods to mitigate these defects: optimizing the atomic layer deposition (ALD) process to reduce bulk trap density and employing high-pressure deuterium annealing (HPDA) to passivate interface trap density. Increasing the ALD process pressure and ozone reactant flow rate facilitates Cp-ligand ozone-induced combustion, thereby reducing film impurities and bulk trap densities. Deuterium (D2) was successfully injected into the entire film and interface, lowering both bulk and interface trap densities. Furthermore, the reduction in trap densities was further improved with high D2 pressure. By modulating the ALD process and adopting HPDA, we achieved reductions in the interface trap density of Al₂O₃, HfO₂, and ZrO₂ by 53.5 %, 93.4 %, and 81.1 %, respectively. These findings indicate that HPDA and optimized ALD processes can enhance the performance and stability of semiconductor devices utilizing high-k materials at low process temperatures.