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Design of the Global Reconstruction Logic in the Belle II Level-1 Trigger system

Authors
Lai, Y.-T.Koga, T.Iwasaki, Y.Ahn, Y.Bae, H.Campajola, M.Cheon, B.G.Cho, H.-E.Ferber, T.Haide, I.Heine, G.Hsu, C.-L.Kiesling, C.Kim, C.-H.Kim, J.B.Kim, K.Kim, S.H.Lee, I.S.Lee, M.J.Liao, Y.P.Lin, J.Little, A.Moon, H.K.Nakazawa, H.Neu, M.Nishida, S.Reuter, L.Savinov, V.Sheng, T.-A.Shiu, J.-G.Sue, Y.Unger, K.Unno, Y.Won, E.Xu, Z.
Issue Date
Sep-2025
Publisher
Elsevier BV
Keywords
B factory; FPGA; Trigger
Citation
Nuclear Instruments and Methods in Physics Research, Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, v.1078, pp 1 - 10
Pages
10
Indexed
SCIE
SCOPUS
Journal Title
Nuclear Instruments and Methods in Physics Research, Section A: Accelerators, Spectrometers, Detectors and Associated Equipment
Volume
1078
Start Page
1
End Page
10
URI
https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/207537
DOI
10.1016/j.nima.2025.170577
ISSN
0168-9002
1872-9576
Abstract
The Belle II experiment is designed to search for physics beyond the Standard Model by investigating rare decays at the SuperKEKB e+e− collider. Owing to the significant beam background at high luminosity, the data acquisition system employs a hardware-based Level-1 Trigger to reduce the readout data throughput by selecting collision events of interest in real time. The Belle II Level-1 Trigger system utilizes FPGAs to reconstruct various detector observables from the raw data for trigger decision-making. The Level-1 trigger rate is limited to 30 kHz at the maximum expected instantaneous luminosity of SuperKEKB. To ensure reliable B physics measurements, the trigger efficiency for hadronic events, specifically, e+e−→BB̄ and e+e−→qq̄ processes, where q=u,d,s,c, must be close to 100%. The Global Reconstruction Logic receives these observables from four sub-trigger systems and provides a global summary for the final trigger decision. Its logic encompasses charged particle tracking, matching between sub-triggers, and the identification of special event topologies associated with low-multiplicity decays. This article discusses the hardware devices, FPGA firmware, integration with peripheral systems, and the design and performance of the trigger algorithms implemented within the Global Reconstruction Logic.
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