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Hope: An Efficient Accelerator With Head-Wise Overlap Processing for Sparse Attention in Vision Transformer
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Heo, Jihyeon | - |
| dc.contributor.author | Rho, Soomin | - |
| dc.contributor.author | Kim, Kwangrae | - |
| dc.contributor.author | Chung, Ki-Seok | - |
| dc.date.accessioned | 2025-07-04T06:00:07Z | - |
| dc.date.available | 2025-07-04T06:00:07Z | - |
| dc.date.issued | 2025-06 | - |
| dc.identifier.issn | 2167-9657 | - |
| dc.identifier.issn | 2473-4683 | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/207993 | - |
| dc.description.abstract | Vision Transformers (ViTs) have revolutionized computer vision tasks with superior performance, but their quadratic computational complexity in self-attention remains a critical bottleneck. Sparse attention mitigates this issue by avoiding unnecessary computations, but existing accelerators enforce the sequential execution of QKV generation and sparse attention computations, which hinders execution time improvement. In this paper, we propose HOPE, a novel sparse attention accelerator for ViTs. HOPE accelerator introduces a head-wise overlap scheduling method and a new vector processing unit called SaVPU. The SaVPU augments conventional non-linear operation units with minimal hardware overhead to efficiently process sparse attention, such as SDDMM and SpMM operations. The head-wise overlap scheduling method enables concurrent execution of QKV generation and sparse attention computations. This overlapping execution significantly reduces latency. Extensive experiments on ViT models with sparsity levels between 60 % and 90 % demonstrate that HOPE achieves up to a 1.4× speedup (1.2× on average) over the state-of-the-art ViTCoD accelerator while incurring only 1.25 % additional hardware area. These results confirm the HOPE accelerator achieves significant speedup with minimal hardware overhead. | - |
| dc.format.extent | 6 | - |
| dc.language | 영어 | - |
| dc.language.iso | ENG | - |
| dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
| dc.title | Hope: An Efficient Accelerator With Head-Wise Overlap Processing for Sparse Attention in Vision Transformer | - |
| dc.type | Article | - |
| dc.publisher.location | 미국 | - |
| dc.identifier.doi | 10.1109/COOLCHIPS65488.2025.11018597 | - |
| dc.identifier.scopusid | 2-s2.0-105008495116 | - |
| dc.identifier.wosid | 001549674500011 | - |
| dc.identifier.bibliographicCitation | IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2025 - Proceedings, pp 1 - 6 | - |
| dc.citation.title | IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2025 - Proceedings | - |
| dc.citation.startPage | 1 | - |
| dc.citation.endPage | 6 | - |
| dc.type.docType | Proceedings Paper | - |
| dc.description.isOpenAccess | N | - |
| dc.description.journalRegisteredClass | scopus | - |
| dc.relation.journalResearchArea | Computer Science | - |
| dc.relation.journalResearchArea | Engineering | - |
| dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture | - |
| dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
| dc.subject.keywordPlus | Array processing | - |
| dc.subject.keywordPlus | Computer hardware | - |
| dc.subject.keywordPlus | Computer vision | - |
| dc.subject.keywordPlus | Concurrency control | - |
| dc.subject.keywordPlus | Particle accelerators | - |
| dc.subject.keywordPlus | Program processors | - |
| dc.subject.keywordAuthor | Hardware Accelerator | - |
| dc.subject.keywordAuthor | Sparse Attention | - |
| dc.subject.keywordAuthor | Vision Transformer | - |
| dc.identifier.url | https://ieeexplore.ieee.org/document/11018597 | - |
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