Process-Portable Layout Generation of High-Speed Digital Circuit Using Standard Cells in FinFET

Abstract

This paper presents a generator-based layout design methodology that leverages foundry-standard cells to produce area-efficient and design-rule-check (DRC) clean high-speed custom digital circuits. The proposed approach facilitates guided structural placement and routing based on DRC-clean grids extracted from standard cells, offering enhanced fine-tuning and interactive placement and routing capabilities compared to conventional digital synthesis methods. Unlike previous generator-based layout generation methods, the proposed approach employs area-and power-efficient standard cells, achieving reductions of 77.8% in area and 28.57% in power, respectively, compared to a full-custom design in the identical process node, while maintaining customization capabilities and layout quality.