CENNA: Cost-Effective Neural Network Accelerator
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Park, Sang-Soo | - |
dc.contributor.author | Chung, Ki Seok | - |
dc.date.accessioned | 2021-07-30T04:54:52Z | - |
dc.date.available | 2021-07-30T04:54:52Z | - |
dc.date.created | 2021-05-12 | - |
dc.date.issued | 2020-01 | - |
dc.identifier.issn | 2079-9292 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/2092 | - |
dc.description.abstract | Convolutional neural networks (CNNs) are widely adopted in various applications. State-of-the-art CNN models deliver excellent classification performance, but they require a large amount of computation and data exchange because they typically employ many processing layers. Among these processing layers, convolution layers, which carry out many multiplications and additions, account for a major portion of computation and memory access. Therefore, reducing the amount of computation and memory access is the key for high-performance CNNs. In this study, we propose a cost-effective neural network accelerator, named CENNA, whose hardware cost is reduced by employing a cost-centric matrix multiplication that employs both Strassen's multiplication and a naive multiplication. Furthermore, the convolution method using the proposed matrix multiplication can minimize data movement by reusing both the feature map and the convolution kernel without any additional control logic. In terms of throughput, power consumption, and silicon area, the efficiency of CENNA is up to 88 times higher than that of conventional designs for the CNN inference. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | MDPI | - |
dc.title | CENNA: Cost-Effective Neural Network Accelerator | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Chung, Ki Seok | - |
dc.identifier.doi | 10.3390/electronics9010134 | - |
dc.identifier.scopusid | 2-s2.0-85078249288 | - |
dc.identifier.wosid | 000516827000134 | - |
dc.identifier.bibliographicCitation | ELECTRONICS, v.9, no.1, pp.1 - 19 | - |
dc.relation.isPartOf | ELECTRONICS | - |
dc.citation.title | ELECTRONICS | - |
dc.citation.volume | 9 | - |
dc.citation.number | 1 | - |
dc.citation.startPage | 1 | - |
dc.citation.endPage | 19 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | Y | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalResearchArea | Physics | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Information Systems | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
dc.subject.keywordAuthor | convolutional neural network (CNN) | - |
dc.subject.keywordAuthor | neural network accelerator | - |
dc.subject.keywordAuthor | neural processing unit (NPU) | - |
dc.subject.keywordAuthor | CNN inference | - |
dc.identifier.url | https://www.mdpi.com/2079-9292/9/1/134 | - |
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