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The 3D Monolithically Integrated Hardware Based Neural System with Enhanced Memory Window of the Volatile and Non-Volatile Devices
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Jeon, Yu-Rim | - |
| dc.contributor.author | Seo, Donguk | - |
| dc.contributor.author | Lee, Yoonmyung | - |
| dc.contributor.author | Akinwande, Deji | - |
| dc.contributor.author | Choi, Changhwan | - |
| dc.date.accessioned | 2025-12-11T01:30:53Z | - |
| dc.date.available | 2025-12-11T01:30:53Z | - |
| dc.date.issued | 2024-08 | - |
| dc.identifier.issn | 2198-3844 | - |
| dc.identifier.issn | 2198-3844 | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/209724 | - |
| dc.description.abstract | 3D neuromorphic hardware system is first demonstrated in neuromorphic application as on-chip level by integrating array devices with CMOS circuits after wafer bonding (WB) and interconnection process. The memory window of synaptic device is degraded after WB and 3 Dimesional (3D) integration due to process defects and thermal stress. To address this degradation, Ag diffusion in materials of Ta2O5 and HfO2 is studied in a volatile memristor, furthermore, the interconnection and gate metal Ru are investigated to reduce defective traps of gate interface in non-volatile memory devices. As a result, a memory window is improved over 106 in both types of devices. Improved and 3D integrated 12 × 14 array devices are identified in the synaptic characteristics according to the change of the synaptic weight from the interconnected Test Element Group (TEG) of the Complementary Metal Oxide Semiconductor (CMOS) circuits. The trained array devices present recognizable image of letters, achieving an accuracy rate of 92% when utilizing a convolutional neural network, comparing the normalized accuracy of 93% achieved by an ideal synapse device. This study proposes to modulate the memory windows up to 106 in an integrated hardware-based neural system, considering the possibility of device degradation in both volatile and non-volatile memory devices demonstrated by the hardware neural system. | - |
| dc.format.extent | 10 | - |
| dc.language | 영어 | - |
| dc.language.iso | ENG | - |
| dc.publisher | Wiley-VCH Verlag | - |
| dc.title | The 3D Monolithically Integrated Hardware Based Neural System with Enhanced Memory Window of the Volatile and Non-Volatile Devices | - |
| dc.type | Article | - |
| dc.publisher.location | 미국 | - |
| dc.identifier.doi | 10.1002/advs.202402667 | - |
| dc.identifier.scopusid | 2-s2.0-85196115864 | - |
| dc.identifier.wosid | 001247907200001 | - |
| dc.identifier.bibliographicCitation | Advanced Science, v.11, no.31, pp 1 - 10 | - |
| dc.citation.title | Advanced Science | - |
| dc.citation.volume | 11 | - |
| dc.citation.number | 31 | - |
| dc.citation.startPage | 1 | - |
| dc.citation.endPage | 10 | - |
| dc.type.docType | Article; Early Access | - |
| dc.description.isOpenAccess | Y | - |
| dc.description.journalRegisteredClass | scie | - |
| dc.description.journalRegisteredClass | scopus | - |
| dc.relation.journalResearchArea | Chemistry | - |
| dc.relation.journalResearchArea | Science & Technology - Other Topics | - |
| dc.relation.journalResearchArea | Materials Science | - |
| dc.relation.journalWebOfScienceCategory | Chemistry, Multidisciplinary | - |
| dc.relation.journalWebOfScienceCategory | Nanoscience & Nanotechnology | - |
| dc.relation.journalWebOfScienceCategory | Materials Science, Multidisciplinary | - |
| dc.subject.keywordPlus | Atomic layer deposition | - |
| dc.subject.keywordPlus | CMOS integrated circuits | - |
| dc.subject.keywordPlus | Convolution | - |
| dc.subject.keywordPlus | Convolutional neural networks | - |
| dc.subject.keywordPlus | Defects | - |
| dc.subject.keywordPlus | Dynamic random access storage | - |
| dc.subject.keywordPlus | Hafnium oxides | - |
| dc.subject.keywordPlus | Integrated circuit interconnects | - |
| dc.subject.keywordPlus | MOS devices | - |
| dc.subject.keywordPlus | Oxide semiconductors | - |
| dc.subject.keywordPlus | Silicon wafers | - |
| dc.subject.keywordPlus | Tantalum oxides | - |
| dc.subject.keywordPlus | Three dimensional integrated circuits | - |
| dc.subject.keywordPlus | Wafer bonding | - |
| dc.subject.keywordAuthor | 3D neuromorphic system | - |
| dc.subject.keywordAuthor | CMOS integration | - |
| dc.subject.keywordAuthor | convolutional neural network | - |
| dc.subject.keywordAuthor | high k metal oxide | - |
| dc.subject.keywordAuthor | RRAM | - |
| dc.subject.keywordAuthor | synaptic device | - |
| dc.subject.keywordAuthor | transistor | - |
| dc.subject.keywordAuthor | wafer bonding | - |
| dc.identifier.url | https://onlinelibrary.wiley.com/doi/10.1002/advs.202402667 | - |
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