Configurable Kernel Map Implementation in Memristor Crossbar for Convolution Neural Network

Abstract

This study experimentally verifies a configurable convolutional neural network implementation in a 48 x 48 memristor crossbar array. It allows the number of convolution reading cycles to be adjusted based on design demands, such as area or time constraints. This adaptability can be achieved by modifying the area of kernel weights on the array, enabling a balance between time and area efficiency. A detailed algorithm for the configurable convolution scheme is presented, taking into account factors such as array size, feature map size, and cycle limits. Also, the experimental validation using a binary 12 x 12 MNIST dataset demonstrates the practical applicability of our scheme. By varying the number of cycles per inference (Ncycle), this study analyzes how different array sizes can affect performance, confirming the relationship between the total number of cells (Ncell) and cycles. Larger Ncycle values can result in the increased usage of faulty devices, leading to more distorted feature map pixels. Additionally, it analyzes the robustness of the scheme to weight errors, finding that longer cycles are less robust due to more frequent reads on critical fault devices within the crossbar, causing accuracy degradation.